AR405.h 9.5 KB

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  1. /*
  2. * (C) Copyright 2001-2004
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_AR405 1 /* ...on a AR405 board */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  36. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  37. #define CONFIG_BOARD_TYPES 1 /* support board types */
  38. #define CONFIG_BAUDRATE 9600
  39. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  40. #if 1
  41. #define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
  42. #else
  43. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  44. #endif
  45. #if 0
  46. #define CONFIG_BOOTARGS "root=/dev/nfs " \
  47. "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
  48. "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
  49. #else
  50. #define CONFIG_BOOTARGS "root=/dev/hda1 " \
  51. "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
  52. #endif
  53. #define CONFIG_PREBOOT /* enable preboot variable */
  54. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  55. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  56. #define CONFIG_MII 1 /* MII PHY management */
  57. #define CONFIG_PHY_ADDR 0 /* PHY address */
  58. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  59. /*
  60. * BOOTP options
  61. */
  62. #define CONFIG_BOOTP_BOOTFILESIZE
  63. #define CONFIG_BOOTP_BOOTPATH
  64. #define CONFIG_BOOTP_GATEWAY
  65. #define CONFIG_BOOTP_HOSTNAME
  66. /*
  67. * Command line configuration.
  68. */
  69. #include <config_cmd_default.h>
  70. #define CONFIG_CMD_DHCP
  71. #define CONFIG_CMD_PCI
  72. #define CONFIG_CMD_IRQ
  73. #define CONFIG_CMD_ELF
  74. #define CONFIG_CMD_MII
  75. #define CONFIG_CMD_PING
  76. #define CONFIG_CMD_BSP
  77. #undef CONFIG_WATCHDOG /* watchdog disabled */
  78. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  79. /*
  80. * Miscellaneous configurable options
  81. */
  82. #define CFG_LONGHELP /* undef to save memory */
  83. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  84. #if defined(CONFIG_CMD_KGDB)
  85. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  86. #else
  87. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  88. #endif
  89. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  90. #define CFG_MAXARGS 16 /* max number of command args */
  91. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  92. #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
  93. #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  94. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  95. #define CONFIG_LOOPW 1 /* enable loopw command */
  96. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  97. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  98. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  99. #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
  100. /* The following table includes the supported baudrates */
  101. #define CFG_BAUDRATE_TABLE \
  102. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  103. 57600, 115200, 230400, 460800, 921600 }
  104. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  105. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  106. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  107. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  108. /*-----------------------------------------------------------------------
  109. * PCI stuff
  110. *-----------------------------------------------------------------------
  111. */
  112. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  113. #define PCI_HOST_FORCE 1 /* configure as pci host */
  114. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  115. #define CONFIG_PCI /* include pci support */
  116. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  117. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  118. /* resource configuration */
  119. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  120. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  121. #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  122. #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  123. #define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
  124. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  125. #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  126. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  127. #define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */
  128. #define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
  129. #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  130. /*-----------------------------------------------------------------------
  131. * Start addresses for the final memory configuration
  132. * (Set up by the startup code)
  133. * Please note that CFG_SDRAM_BASE _must_ start at 0
  134. */
  135. #define CFG_SDRAM_BASE 0x00000000
  136. #define CFG_FLASH_BASE 0xFFFC0000
  137. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  138. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  139. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  140. /*
  141. * For booting Linux, the board info and command line data
  142. * have to be in the first 8 MB of memory, since this is
  143. * the maximum mapped by the Linux kernel during initialization.
  144. */
  145. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  146. /*-----------------------------------------------------------------------
  147. * FLASH organization
  148. */
  149. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  150. #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  151. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  152. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  153. #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  154. #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  155. #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  156. /*
  157. * The following defines are added for buggy IOP480 byte interface.
  158. * All other boards should use the standard values (CPCI405 etc.)
  159. */
  160. #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
  161. #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
  162. #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
  163. #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  164. #define CONFIG_ENV_IS_IN_FLASH 1
  165. #define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/
  166. #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
  167. #define CFG_ENV_SIZE 0x04000 /* Size of Environment */
  168. #define CFG_ENV_ADDR_REDUND 0xFFFA0000
  169. #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
  170. /*
  171. * Init Memory Controller:
  172. *
  173. * BR0/1 and OR0/1 (FLASH)
  174. */
  175. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  176. /*-----------------------------------------------------------------------
  177. * External Bus Controller (EBC) Setup
  178. */
  179. /* Memory Bank 0 (Flash Bank 0) initialization */
  180. #define CFG_EBC_PB0AP 0x92015480
  181. #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  182. /* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
  183. #define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
  184. #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  185. /* Memory Bank 2 (Expension Bus) initialization */
  186. #define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
  187. #define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
  188. /* Memory Bank 3 (16552) initialization */
  189. #define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
  190. #define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
  191. /* Memory Bank 4 (FPGA regs) initialization */
  192. #define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
  193. #define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
  194. /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
  195. #define CFG_EBC_PB5AP 0x92015480
  196. #define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
  197. /*-----------------------------------------------------------------------
  198. * Definitions for initial stack pointer and data area (in data cache)
  199. */
  200. #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
  201. #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
  202. #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
  203. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  204. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  205. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  206. /*
  207. * Internal Definitions
  208. *
  209. * Boot Flags
  210. */
  211. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  212. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  213. #endif /* __CONFIG_H */