AMX860.h 10 KB

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  1. /*
  2. * (C) Copyright 2001-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC860 1
  33. #define CONFIG_AMX860 1
  34. #undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
  35. #undef CONFIG_8xx_CONS_SMC2
  36. #define CONFIG_8xx_CONS_SCC2 1
  37. #undef CONFIG_8xx_CONS_NONE
  38. #define CONFIG_BAUDRATE 9600
  39. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  40. #define MPC8XX_FACT 10 /* Multiply by 10 */
  41. #define MPC8XX_XIN 5000000 /* 5 MHz in */
  42. #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  43. #if 0
  44. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  45. #else
  46. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  47. #endif
  48. #define CONFIG_BOOTCOMMAND \
  49. "bootp;" \
  50. "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  51. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
  52. "bootm" /* autoboot command */
  53. #undef CONFIG_BOOTARGS
  54. #undef CONFIG_WATCHDOG /* watchdog disabled */
  55. #define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
  56. #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  57. /*
  58. * Command line configuration.
  59. */
  60. #include <config_cmd_default.h>
  61. #define CONFIG_CMD_DHCP
  62. #define CONFIG_CMD_DATE
  63. #define CONFIG_CMD_NFS
  64. #define CONFIG_CMD_SNTP
  65. #if defined(CONFIG_CMD_KGDB)
  66. #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  67. #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  68. #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  69. #define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
  70. #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
  71. #endif
  72. /*
  73. * BOOTP options
  74. */
  75. #define CONFIG_BOOTP_BOOTFILESIZE
  76. #define CONFIG_BOOTP_BOOTPATH
  77. #define CONFIG_BOOTP_GATEWAY
  78. #define CONFIG_BOOTP_HOSTNAME
  79. #define CONFIG_BOOTP_SUBNETMASK
  80. /*
  81. * Miscellaneous configurable options
  82. */
  83. #define CFG_LONGHELP /* undef to save memory */
  84. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  85. #if defined(CONFIG_CMD_KGDB)
  86. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  87. #else
  88. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  89. #endif
  90. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  91. #define CFG_MAXARGS 16 /* max number of command args */
  92. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  93. #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
  94. #define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
  95. #define CFG_LOAD_ADDR 0x00100000
  96. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  97. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  98. /*
  99. * Low Level Configuration Settings
  100. * (address mappings, register initial values, etc.)
  101. * You should know what you are doing if you make changes here.
  102. */
  103. /*-----------------------------------------------------------------------
  104. * Internal Memory Mapped Register
  105. */
  106. #define CFG_IMMR 0xFF000000
  107. /*-----------------------------------------------------------------------
  108. * Definitions for initial stack pointer and data area (in DPRAM)
  109. */
  110. #define CFG_INIT_RAM_ADDR CFG_IMMR
  111. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  112. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  113. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  114. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  115. /*-----------------------------------------------------------------------
  116. * Start addresses for the final memory configuration
  117. * (Set up by the startup code)
  118. * Please note that CFG_SDRAM_BASE _must_ start at 0
  119. */
  120. #define CFG_SDRAM_BASE 0x00000000
  121. #define CFG_FLASH_BASE 0x40000000
  122. #if defined(DEBUG)
  123. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  124. #else
  125. #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
  126. #endif
  127. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  128. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  129. /*
  130. * U-Boot for AMX board supports two types of memory extension
  131. * modules: one that provides 4 MB flash memory, and another one with
  132. * 16 MB EDO DRAM.
  133. *
  134. * The flash module swaps the CS0 and CS1 signals: if the module is
  135. * installed, CS0 is connected to Flash on the module and CS1 is
  136. * connected to the on-board Flash. This means that you must intall
  137. * U-Boot when the Flash module is plugged in, if you plan to use
  138. * it.
  139. *
  140. * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
  141. * must be defined. The DRAM module uses CS1.
  142. *
  143. * Only one of these modules may be installed at a time. If U-Boot
  144. * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
  145. * work if the Flash extension module is installed instead of the
  146. * DRAM module.
  147. */
  148. #define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */
  149. /*
  150. * For booting Linux, the board info and command line data
  151. * have to be in the first 8 MB of memory, since this is
  152. * the maximum mapped by the Linux kernel during initialization.
  153. *
  154. * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
  155. * (CONFIG_AMX_RAM_EXT)
  156. */
  157. #ifdef CONFIG_AMX_RAM_EXT
  158. # define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  159. #else
  160. # define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */
  161. #endif
  162. /*-----------------------------------------------------------------------
  163. * FLASH organization
  164. */
  165. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  166. #define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
  167. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  168. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  169. #define CONFIG_ENV_IS_IN_FLASH 1
  170. #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  171. #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  172. /*-----------------------------------------------------------------------
  173. * Cache Configuration
  174. */
  175. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  176. #if defined(CONFIG_CMD_KGDB)
  177. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  178. #endif
  179. /*-----------------------------------------------------------------------
  180. * SYPCR - System Protection Control 11-9
  181. * SYPCR can only be written once after reset!
  182. *-----------------------------------------------------------------------
  183. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  184. */
  185. #if defined(CONFIG_WATCHDOG)
  186. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  187. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  188. #else
  189. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  190. #endif
  191. /*-----------------------------------------------------------------------
  192. * SIUMCR - SIU Module Configuration 11-6
  193. *-----------------------------------------------------------------------
  194. * PCMCIA config., multi-function pin tri-state
  195. */
  196. #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  197. /*-----------------------------------------------------------------------
  198. * TBSCR - Time Base Status and Control 11-26
  199. *-----------------------------------------------------------------------
  200. * Clear Reference Interrupt Status, Timebase freezing enabled
  201. */
  202. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
  203. /*-----------------------------------------------------------------------
  204. * PISCR - Periodic Interrupt Status and Control 11-31
  205. *-----------------------------------------------------------------------
  206. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  207. */
  208. #define CFG_PISCR (PISCR_PS | PISCR_PITF)
  209. /*-----------------------------------------------------------------------
  210. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  211. *-----------------------------------------------------------------------
  212. * set the PLL, the low-power modes and the reset control (15-29)
  213. */
  214. #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
  215. PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  216. /*-----------------------------------------------------------------------
  217. * SCCR - System Clock and reset Control Register 15-27
  218. *-----------------------------------------------------------------------
  219. * Set clock output, timebase and RTC source and divider,
  220. * power management and some other internal clocks
  221. */
  222. #define SCCR_MASK SCCR_EBDF11
  223. #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
  224. #define CFG_DER 0
  225. /*
  226. * Init Memory Controller:
  227. *
  228. * BR0/1 and OR0/1 (FLASH)
  229. */
  230. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  231. #ifndef CONFIG_AMX_RAM_EXT
  232. #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
  233. #endif
  234. #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  235. #define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
  236. /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
  237. /* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */
  238. #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
  239. #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  240. #define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */
  241. #define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
  242. #ifndef CONFIG_AMX_RAM_EXT
  243. #define CFG_OR1_REMAP CFG_OR0_REMAP
  244. #define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */
  245. #define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */
  246. #endif
  247. /* DSP ("Glue") Xilinx */
  248. #define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
  249. #define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
  250. /*
  251. * Internal Definitions
  252. *
  253. * Boot Flags
  254. */
  255. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  256. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  257. #endif /* __CONFIG_H */