ADNPESC1.h 22 KB

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  1. /*
  2. * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3. * Stephan Linz <linz@li-pro.net>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /***********************************************************************
  26. * Include the whole NIOS CPU configuration.
  27. *
  28. * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
  29. *
  30. ***********************************************************************/
  31. #if defined(CONFIG_NIOS_BASE_32)
  32. #include <configs/ADNPESC1_base_32.h>
  33. #else
  34. #error *** CFG_ERROR: you have to setup right NIOS CPU configuration
  35. #endif
  36. /*------------------------------------------------------------------------
  37. * BOARD/CPU -- TOP-LEVEL
  38. *----------------------------------------------------------------------*/
  39. #define CONFIG_NIOS 1 /* NIOS-32 core */
  40. #define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */
  41. #define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
  42. #define CFG_HZ 1000 /* 1 msec time tick */
  43. #undef CFG_CLKS_IN_HZ
  44. #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
  45. /*------------------------------------------------------------------------
  46. * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  47. *----------------------------------------------------------------------*/
  48. #if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
  49. #define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
  50. #define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
  51. #else
  52. #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
  53. #endif
  54. #if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
  55. #define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
  56. #define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
  57. #else
  58. #undef CFG_SRAM_BASE
  59. #undef CFG_SRAM_SIZE
  60. #endif
  61. #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
  62. /*------------------------------------------------------------------------
  63. * MEMORY ORGANIZATION - For the most part, you can put things pretty
  64. * much anywhere. This is pretty flexible for Nios. So here we make some
  65. * arbitrary choices & assume that the monitor is placed at the end of
  66. * a memory resource (so you must make sure TEXT_BASE is chosen
  67. * appropriately -- this is very important if you plan to move your
  68. * memory to another place as configured at this time !!!).
  69. *
  70. * -The heap is placed below the monitor.
  71. * -Global data is placed below the heap.
  72. * -The stack is placed below global data (&grows down).
  73. *----------------------------------------------------------------------*/
  74. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
  75. #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
  76. #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  77. #define CFG_MONITOR_BASE TEXT_BASE
  78. #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  79. #define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  80. #define CFG_INIT_SP CFG_GBL_DATA_OFFSET
  81. /*------------------------------------------------------------------------
  82. * FLASH (AM29LV065D)
  83. *----------------------------------------------------------------------*/
  84. #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
  85. #define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
  86. #define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
  87. #define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
  88. #define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
  89. #define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
  90. #define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
  91. #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */
  92. #else
  93. #error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
  94. #endif
  95. /*------------------------------------------------------------------------
  96. * ENVIRONMENT
  97. *----------------------------------------------------------------------*/
  98. #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
  99. #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
  100. /* Mem addr of environment */
  101. #if defined(CONFIG_NIOS_BASE_32)
  102. #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
  103. #else
  104. #error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
  105. #endif
  106. #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
  107. #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
  108. #else
  109. #define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */
  110. #endif
  111. /*------------------------------------------------------------------------
  112. * NIOS APPLICATION CODE BASE AREA
  113. *----------------------------------------------------------------------*/
  114. #if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
  115. #define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100"
  116. #define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000"
  117. #define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c"
  118. #define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff"
  119. #define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000"
  120. #define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff"
  121. #else
  122. #error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
  123. #endif
  124. #define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios"
  125. /*------------------------------------------------------------------------
  126. * BOOT ENVIRONMENT
  127. *----------------------------------------------------------------------*/
  128. #ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
  129. #define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; "
  130. #define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; "
  131. #else
  132. #define CFG_ADNPESC1_SLED_BOOT_OFF
  133. #define CFG_ADNPESC1_SLED_RED_BLINK
  134. #endif
  135. #define CONFIG_BOOTDELAY 5
  136. #define CONFIG_BOOTCOMMAND \
  137. "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \
  138. "then " \
  139. "wd off; " \
  140. CFG_ADNPESC1_SLED_BOOT_OFF \
  141. "go $appl_entry_addr; " \
  142. "else " \
  143. CFG_ADNPESC1_SLED_RED_BLINK \
  144. "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
  145. "echo *** invalid application at $appl_entry_addr; " \
  146. "echo *** stop bootup...; " \
  147. "fi"
  148. /*------------------------------------------------------------------------
  149. * EXTRA ENVIRONMENT
  150. *----------------------------------------------------------------------*/
  151. #ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
  152. #define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; "
  153. #define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; "
  154. #else
  155. #define CFG_ADNPESC1_SLED_YELLO_ON
  156. #define CFG_ADNPESC1_SLED_YELLO_OFF
  157. #endif
  158. #define CONFIG_EXTRA_ENV_SETTINGS \
  159. "update_allowed=0\0" \
  160. "update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \
  161. "appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \
  162. "appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \
  163. "appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \
  164. "appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \
  165. "appl_name=ADNPESC1/base32/linux.bin\0" \
  166. "appl_update=" \
  167. "if itest.b $update_allowed != 0; " \
  168. "then " \
  169. CFG_ADNPESC1_SLED_YELLO_ON \
  170. "tftp $update_load_addr $appl_name; " \
  171. "protect off $appl_entry_addr $appl_end_addr; " \
  172. "era $appl_entry_addr $appl_end_addr; " \
  173. "cp.b $update_load_addr $appl_entry_addr $filesize; "\
  174. CFG_ADNPESC1_SLED_YELLO_OFF \
  175. "else " \
  176. "echo *** update not allowed (update_allowed=$update_allowed); "\
  177. "fi\0" \
  178. "fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \
  179. "fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \
  180. "fs_name=ADNPESC1/base32/romfs.img\0" \
  181. "fs_update=" \
  182. "if itest.b $update_allowed != 0; " \
  183. "then " \
  184. CFG_ADNPESC1_SLED_YELLO_ON \
  185. "tftp $update_load_addr $fs_name; " \
  186. "protect off $fs_base_addr $fs_end_addr; " \
  187. "era $fs_base_addr $fs_end_addr; " \
  188. "cp.b $update_load_addr $fs_base_addr $filesize; "\
  189. CFG_ADNPESC1_SLED_YELLO_OFF \
  190. "else " \
  191. "echo *** update not allowed (update_allowed=$update_allowed); "\
  192. "fi\0" \
  193. "uboot_name=ADNPESC1/base32/u-boot.bin\0" \
  194. "uboot_loadnrun=" \
  195. "if ping $serverip; " \
  196. "then " \
  197. CFG_ADNPESC1_SLED_YELLO_ON \
  198. "tftp $update_load_addr $uboot_name; " \
  199. "wd off; " \
  200. "go $update_load_addr; " \
  201. "else " \
  202. "echo *** missing connection to $serverip; " \
  203. "echo *** check your network and try again...; "\
  204. "fi\0"
  205. /*------------------------------------------------------------------------
  206. * CONSOLE
  207. *----------------------------------------------------------------------*/
  208. #if (CFG_NIOS_CPU_UART_NUMS != 0)
  209. #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
  210. #if (CFG_NIOS_CPU_UART0_BR != 0)
  211. #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
  212. #define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
  213. #else
  214. #undef CFG_NIOS_FIXEDBAUD
  215. #define CONFIG_BAUDRATE 115200
  216. #endif
  217. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  218. #else
  219. #error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
  220. #endif
  221. /*------------------------------------------------------------------------
  222. * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
  223. * so an avalon bus timer is required.
  224. *----------------------------------------------------------------------*/
  225. #if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
  226. #if (CFG_NIOS_CPU_TICK_TIMER == 0)
  227. #define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
  228. #define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
  229. #if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
  230. #if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
  231. #define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
  232. #else
  233. #error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
  234. #endif
  235. #undef CFG_NIOS_TMRCNT /* no preloadable counter value */
  236. #elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
  237. #if (CFG_HZ <= 1000)
  238. #define CFG_NIOS_TMRMS (1000 / CFG_HZ)
  239. #else
  240. #error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
  241. #endif
  242. #define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
  243. #else
  244. #error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
  245. #endif
  246. #elif (CFG_NIOS_CPU_TICK_TIMER == 1)
  247. #define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
  248. #define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
  249. #if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
  250. #if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
  251. #define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
  252. #else
  253. #error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
  254. #endif
  255. #undef CFG_NIOS_TMRCNT /* no preloadable counter value */
  256. #elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
  257. #if (CFG_HZ <= 1000)
  258. #define CFG_NIOS_TMRMS (1000 / CFG_HZ)
  259. #else
  260. #error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
  261. #endif
  262. #define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
  263. #else
  264. #error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
  265. #endif
  266. #endif /* CFG_NIOS_CPU_TICK_TIMER */
  267. #else
  268. #error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
  269. #endif
  270. /*------------------------------------------------------------------------
  271. * WATCHDOG (or better MAX823 supervisory circuite access)
  272. *----------------------------------------------------------------------*/
  273. #define CONFIG_HW_WATCHDOG 1 /* board specific WD */
  274. #ifdef CONFIG_HW_WATCHDOG
  275. /* MAX823 supervisor -- watchdog enable port at: */
  276. #if (CFG_NIOS_CPU_WDENA_PIO == 0)
  277. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
  278. #elif (CFG_NIOS_CPU_WDENA_PIO == 1)
  279. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
  280. #elif (CFG_NIOS_CPU_WDENA_PIO == 2)
  281. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
  282. #elif (CFG_NIOS_CPU_WDENA_PIO == 3)
  283. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
  284. #elif (CFG_NIOS_CPU_WDENA_PIO == 4)
  285. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
  286. #elif (CFG_NIOS_CPU_WDENA_PIO == 5)
  287. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
  288. #elif (CFG_NIOS_CPU_WDENA_PIO == 6)
  289. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
  290. #elif (CFG_NIOS_CPU_WDENA_PIO == 7)
  291. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
  292. #elif (CFG_NIOS_CPU_WDENA_PIO == 8)
  293. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
  294. #elif (CFG_NIOS_CPU_WDENA_PIO == 9)
  295. #define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
  296. #else
  297. #error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
  298. #endif
  299. /* MAX823 supervisor -- watchdog trigger port at: */
  300. #if (CFG_NIOS_CPU_WDTOG_PIO == 0)
  301. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
  302. #elif (CFG_NIOS_CPU_WDTOG_PIO == 1)
  303. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
  304. #elif (CFG_NIOS_CPU_WDTOG_PIO == 2)
  305. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
  306. #elif (CFG_NIOS_CPU_WDTOG_PIO == 3)
  307. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
  308. #elif (CFG_NIOS_CPU_WDTOG_PIO == 4)
  309. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
  310. #elif (CFG_NIOS_CPU_WDTOG_PIO == 5)
  311. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
  312. #elif (CFG_NIOS_CPU_WDTOG_PIO == 6)
  313. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
  314. #elif (CFG_NIOS_CPU_WDTOG_PIO == 7)
  315. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
  316. #elif (CFG_NIOS_CPU_WDTOG_PIO == 8)
  317. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
  318. #elif (CFG_NIOS_CPU_WDTOG_PIO == 9)
  319. #define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
  320. #else
  321. #error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
  322. #endif
  323. #if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */
  324. #define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */
  325. #define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */
  326. #define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/
  327. #else
  328. #error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
  329. #endif
  330. #endif /* CONFIG_HW_WATCHDOG */
  331. /*------------------------------------------------------------------------
  332. * SERIAL PERIPHAREL INTERFACE
  333. *----------------------------------------------------------------------*/
  334. #if (CFG_NIOS_CPU_SPI_NUMS == 1)
  335. #define CONFIG_NIOS_SPI 1 /* SPI support active */
  336. #define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0
  337. #define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS
  338. #define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
  339. #define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
  340. #else
  341. #undef CONFIG_NIOS_SPI /* NO SPI support */
  342. #endif
  343. /*------------------------------------------------------------------------
  344. * Ethernet -- needs work!
  345. *----------------------------------------------------------------------*/
  346. #if (CFG_NIOS_CPU_LAN_NUMS == 1)
  347. #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
  348. #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
  349. #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
  350. #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
  351. #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
  352. #define CONFIG_SMC_USE_32_BIT 1
  353. #else /* no */
  354. #undef CONFIG_SMC_USE_32_BIT
  355. #endif
  356. #elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
  357. /********************************************/
  358. /* !!! CS8900 is __not__ tested on NIOS !!! */
  359. /********************************************/
  360. #define CONFIG_DRIVER_CS8900 /* Using CS8900 */
  361. #define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
  362. #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
  363. #undef CS8900_BUS16
  364. #define CS8900_BUS32 1
  365. #else /* no */
  366. #define CS8900_BUS16 1
  367. #undef CS8900_BUS32
  368. #endif
  369. #else
  370. #error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
  371. #endif
  372. #define CONFIG_ETHADDR 02:80:ae:20:60:6f
  373. #define CONFIG_NETMASK 255.255.255.248
  374. #define CONFIG_IPADDR 192.168.161.84
  375. #define CONFIG_SERVERIP 192.168.161.85
  376. #else
  377. #error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
  378. #endif
  379. /*------------------------------------------------------------------------
  380. * STATUS LEDs
  381. *----------------------------------------------------------------------*/
  382. #if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
  383. #if (CFG_NIOS_CPU_LED_PIO == 0)
  384. #define STATUS_LED_BASE CFG_NIOS_CPU_PIO0
  385. #define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS
  386. #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  387. #if (CFG_NIOS_CPU_PIO0_TYPE == 1)
  388. #define STATUS_LED_WRONLY 1
  389. #else
  390. #undef STATUS_LED_WRONLY
  391. #endif
  392. #elif (CFG_NIOS_CPU_LED_PIO == 1)
  393. #define STATUS_LED_BASE CFG_NIOS_CPU_PIO1
  394. #define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS
  395. #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  396. #if (CFG_NIOS_CPU_PIO1_TYPE == 1)
  397. #define STATUS_LED_WRONLY 1
  398. #else
  399. #undef STATUS_LED_WRONLY
  400. #endif
  401. #elif (CFG_NIOS_CPU_LED_PIO == 2)
  402. #define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
  403. #define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
  404. #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  405. #if (CFG_NIOS_CPU_PIO2_TYPE == 1)
  406. #define STATUS_LED_WRONLY 1
  407. #else
  408. #undef STATUS_LED_WRONLY
  409. #endif
  410. #elif (CFG_NIOS_CPU_LED_PIO == 3)
  411. #error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
  412. #elif (CFG_NIOS_CPU_LED_PIO == 4)
  413. #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
  414. #elif (CFG_NIOS_CPU_LED_PIO == 5)
  415. #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
  416. #elif (CFG_NIOS_CPU_LED_PIO == 6)
  417. #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
  418. #elif (CFG_NIOS_CPU_LED_PIO == 7)
  419. #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
  420. #elif (CFG_NIOS_CPU_LED_PIO == 8)
  421. #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
  422. #elif (CFG_NIOS_CPU_LED_PIO == 9)
  423. #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
  424. #else
  425. #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
  426. #endif
  427. #define CONFIG_STATUS_LED 1 /* enable status led driver */
  428. #define STATUS_LED_BIT (1 << 0) /* LED[0] */
  429. #define STATUS_LED_STATE STATUS_LED_BLINKING
  430. #define STATUS_LED_BOOT_STATE STATUS_LED_OFF
  431. #define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */
  432. #define STATUS_LED_BOOT 0 /* boot LED */
  433. #if (STATUS_LED_BITS > 1)
  434. #define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
  435. #define STATUS_LED_STATE1 STATUS_LED_OFF
  436. #define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */
  437. #define STATUS_LED_RED 1 /* fail LED */
  438. #endif
  439. #if (STATUS_LED_BITS > 2)
  440. #define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
  441. #define STATUS_LED_STATE2 STATUS_LED_OFF
  442. #define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */
  443. #define STATUS_LED_YELLOW 2 /* info LED */
  444. #endif
  445. #if (STATUS_LED_BITS > 3)
  446. #define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
  447. #define STATUS_LED_STATE3 STATUS_LED_OFF
  448. #define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */
  449. #define STATUS_LED_GREEN 3 /* info LED */
  450. #endif
  451. #define STATUS_LED_PAR 1 /* makes status_led.h happy */
  452. #endif /* CFG_NIOS_CPU_PIO_NUMS */
  453. /*------------------------------------------------------------------------
  454. * Diagnostics / Power On Self Tests
  455. *----------------------------------------------------------------------*/
  456. #define CONFIG_POST CFG_POST_RTC
  457. #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  458. /*
  459. * BOOTP options
  460. */
  461. #define CONFIG_BOOTP_BOOTFILESIZE
  462. #define CONFIG_BOOTP_BOOTPATH
  463. #define CONFIG_BOOTP_GATEWAY
  464. #define CONFIG_BOOTP_HOSTNAME
  465. /*
  466. * Command line configuration.
  467. */
  468. #include <config_cmd_default.h>
  469. #define CONFIG_CMD_BSP
  470. #define CONFIG_CMD_CDP
  471. #define CONFIG_CMD_DHCP
  472. #define CONFIG_CMD_DIAG
  473. #define CONFIG_CMD_DISPLAY
  474. #define CONFIG_CMD_EXT2
  475. #define CONFIG_CMD_IMMAP
  476. #define CONFIG_CMD_IRQ
  477. #define CONFIG_CMD_PING
  478. #define CONFIG_CMD_PORTIO
  479. #define CONFIG_CMD_REGINFO
  480. #define CONFIG_CMD_REISER
  481. #define CONFIG_CMD_SAVES
  482. #define CONFIG_CMD_SDRAM
  483. #define CONFIG_CMD_SNTP
  484. #undef CONFIG_CMD_NFS
  485. #undef CONFIG_CMD_XIMG
  486. #if (CFG_NIOS_CPU_SPI_NUMS == 1)
  487. #define CONFIG_CMD_DATE
  488. #define CONFIG_CMD_SPI
  489. #endif
  490. /*------------------------------------------------------------------------
  491. * KGDB
  492. *----------------------------------------------------------------------*/
  493. #if defined(CONFIG_CMD_KGDB)
  494. #define CONFIG_KGDB_BAUDRATE 9600
  495. #endif
  496. /*------------------------------------------------------------------------
  497. * MISC
  498. *----------------------------------------------------------------------*/
  499. #define CFG_LONGHELP /* undef to save memory */
  500. #define CFG_HUSH_PARSER 1 /* use "hush" command parser
  501. undef to save memory */
  502. #define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */
  503. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  504. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  505. #define CFG_MAXARGS 64 /* max number of command args*/
  506. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  507. #ifdef CFG_HUSH_PARSER
  508. #define CFG_PROMPT_HUSH_PS2 "[]> "
  509. #endif
  510. /* Default load address */
  511. #if (CFG_SRAM_SIZE != 0)
  512. /* default in SRAM */
  513. #define CFG_LOAD_ADDR CFG_SRAM_BASE
  514. #elif (CFG_SDRAM_SIZE != 0)
  515. /* default in SDRAM */
  516. #if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
  517. #if 1
  518. #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
  519. #else
  520. #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000)
  521. #endif
  522. #else
  523. #define CFG_LOAD_ADDR CFG_SDRAM_BASE
  524. #endif
  525. #else
  526. #undef CFG_LOAD_ADDR /* force error break */
  527. #endif
  528. /* MEM test area */
  529. #if (CFG_SDRAM_SIZE != 0)
  530. /* SDRAM begin to stack area (1MB stack) */
  531. #if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
  532. #if 0
  533. #define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
  534. #else
  535. #define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000)
  536. #endif
  537. #else
  538. #define CFG_MEMTEST_START CFG_SDRAM_BASE
  539. #endif
  540. #define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
  541. #define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
  542. #else
  543. #undef CFG_MEMTEST_START /* force error break */
  544. #undef CFG_MEMTEST_END
  545. #endif
  546. /*
  547. * JFFS2 partitions
  548. *
  549. */
  550. /* No command line, one static partition */
  551. #undef CONFIG_JFFS2_CMDLINE
  552. #define CONFIG_JFFS2_DEV "nor"
  553. #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
  554. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  555. /* mtdparts command line support */
  556. /*
  557. #define CONFIG_JFFS2_CMDLINE
  558. #define MTDIDS_DEFAULT ""
  559. #define MTDPARTS_DEFAULT ""
  560. */
  561. #endif /* __CONFIG_H */