flash.c 14 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/inca-ip.h>
  25. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  26. typedef unsigned long FLASH_PORT_WIDTH;
  27. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  28. #define FLASH_ID_MASK 0xFFFFFFFF
  29. #define FPW FLASH_PORT_WIDTH
  30. #define FPWV FLASH_PORT_WIDTHV
  31. #define ORMASK(size) ((-size) & OR_AM_MSK)
  32. #define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
  33. /* FLASH29 command register addresses */
  34. #define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555)
  35. #define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa)
  36. #define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555)
  37. #define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555)
  38. #define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa)
  39. #define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555)
  40. /* FLASH29 command definitions */
  41. #define FLASH29_CMD_FIRST 0xaaaaaaaa
  42. #define FLASH29_CMD_SECOND 0x55555555
  43. #define FLASH29_CMD_FOURTH 0xaaaaaaaa
  44. #define FLASH29_CMD_FIFTH 0x55555555
  45. #define FLASH29_CMD_SIXTH 0x10101010
  46. #define FLASH29_CMD_SECTOR 0x30303030
  47. #define FLASH29_CMD_PROGRAM 0xa0a0a0a0
  48. #define FLASH29_CMD_CHIP_ERASE 0x80808080
  49. #define FLASH29_CMD_READ_RESET 0xf0f0f0f0
  50. #define FLASH29_CMD_AUTOSELECT 0x90909090
  51. #define FLASH29_CMD_READ 0x70707070
  52. #define IN_RAM_CMD_READ 0x1
  53. #define IN_RAM_CMD_WRITE 0x2
  54. #define FLASH_WRITE_CMD ((ulong)(flash_write_cmd) & 0x7)+0xbf008000
  55. #define FLASH_READ_CMD ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
  56. typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
  57. typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
  58. typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
  59. static ulong flash_get_size(FPWV *addr, flash_info_t *info);
  60. static int write_word(flash_info_t *info, FPWV *dest, FPW data);
  61. static void flash_get_offsets(ulong base, flash_info_t *info);
  62. static flash_info_t *flash_get_info(ulong base);
  63. static void load_cmd(ulong cmd);
  64. static ulong in_ram_cmd = 0;
  65. /******************************************************************************
  66. *
  67. * Don't change the program architecture
  68. * This architecture assure the program
  69. * can be relocated to scratch ram
  70. */
  71. static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
  72. {
  73. int i,j;
  74. FPW temp,temp1;
  75. FPWV *str;
  76. str = (FPWV *)string;
  77. j= strLen/4;
  78. if(cmd == FLASH29_CMD_AUTOSELECT)
  79. {
  80. *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
  81. *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
  82. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT;
  83. }
  84. if(cmd == FLASH29_CMD_READ)
  85. {
  86. i = 0;
  87. while(i<j)
  88. {
  89. temp = *pFA++;
  90. temp1 = *(int *)0xa0000000;
  91. *(int *)0xbf0081f8 = temp1 + temp;
  92. *str++ = temp;
  93. i++;
  94. }
  95. }
  96. if(cmd == FLASH29_CMD_READ_RESET)
  97. {
  98. *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
  99. *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
  100. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
  101. }
  102. *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
  103. }
  104. /******************************************************************************
  105. *
  106. * Don't change the program architecture
  107. * This architecture assure the program
  108. * can be relocated to scratch ram
  109. */
  110. static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
  111. {
  112. *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
  113. *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
  114. if (cmd == FLASH29_CMD_SECTOR)
  115. {
  116. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
  117. *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
  118. *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
  119. *pFA = FLASH29_CMD_SECTOR;
  120. }
  121. if (cmd == FLASH29_CMD_SIXTH)
  122. {
  123. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
  124. *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
  125. *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
  126. *(FLASH29_REG_SIXTH_CYCLE) = FLASH29_CMD_SIXTH;
  127. }
  128. if (cmd == FLASH29_CMD_PROGRAM)
  129. {
  130. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_PROGRAM;
  131. *pFA = value;
  132. }
  133. if (cmd == FLASH29_CMD_READ_RESET)
  134. {
  135. *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
  136. }
  137. *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
  138. }
  139. static void load_cmd(ulong cmd)
  140. {
  141. ulong *src;
  142. ulong *dst;
  143. FUNCPTR_CP absEntry;
  144. ulong func;
  145. if (in_ram_cmd & cmd) return;
  146. if (cmd == IN_RAM_CMD_READ)
  147. {
  148. func = (ulong)flash_read_cmd;
  149. }
  150. else
  151. {
  152. func = (ulong)flash_write_cmd;
  153. }
  154. src = (ulong *)(func & 0xfffffff8);
  155. dst = (ulong *)0xbf008000;
  156. absEntry = (FUNCPTR_CP)(0xbf0081d0);
  157. absEntry(src,dst,0x38);
  158. in_ram_cmd = cmd;
  159. }
  160. /*-----------------------------------------------------------------------
  161. * flash_init()
  162. *
  163. * sets up flash_info and returns size of FLASH (bytes)
  164. */
  165. unsigned long flash_init (void)
  166. {
  167. unsigned long size = 0;
  168. int i;
  169. load_cmd(IN_RAM_CMD_READ);
  170. /* Init: no FLASHes known */
  171. for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
  172. ulong flashbase = PHYS_FLASH_1;
  173. ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
  174. /* Disable write protection */
  175. *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
  176. #if 1
  177. memset(&flash_info[i], 0, sizeof(flash_info_t));
  178. #endif
  179. flash_info[i].size =
  180. flash_get_size((FPW *)flashbase, &flash_info[i]);
  181. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  182. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
  183. i, flash_info[i].size);
  184. }
  185. size += flash_info[i].size;
  186. }
  187. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  188. /* monitor protection ON by default */
  189. flash_protect(FLAG_PROTECT_SET,
  190. CFG_MONITOR_BASE,
  191. CFG_MONITOR_BASE+monitor_flash_len-1,
  192. flash_get_info(CFG_MONITOR_BASE));
  193. #endif
  194. #ifdef CONFIG_ENV_IS_IN_FLASH
  195. /* ENV protection ON by default */
  196. flash_protect(FLAG_PROTECT_SET,
  197. CFG_ENV_ADDR,
  198. CFG_ENV_ADDR+CFG_ENV_SIZE-1,
  199. flash_get_info(CFG_ENV_ADDR));
  200. #endif
  201. return size;
  202. }
  203. /*-----------------------------------------------------------------------
  204. */
  205. static void flash_get_offsets (ulong base, flash_info_t *info)
  206. {
  207. int i;
  208. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
  209. && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) {
  210. int bootsect_size[4]; /* number of bytes/boot sector */
  211. int sect_size; /* number of bytes/regular sector */
  212. bootsect_size[0] = 0x00008000;
  213. bootsect_size[1] = 0x00004000;
  214. bootsect_size[2] = 0x00004000;
  215. bootsect_size[3] = 0x00010000;
  216. sect_size = 0x00020000;
  217. /* set sector offsets for bottom boot block type */
  218. for (i = 0; i < info->sector_count; i++) {
  219. info->start[i] = base;
  220. base += i < 4 ? bootsect_size[i] : sect_size;
  221. }
  222. }
  223. }
  224. /*-----------------------------------------------------------------------
  225. */
  226. static flash_info_t *flash_get_info(ulong base)
  227. {
  228. int i;
  229. flash_info_t * info;
  230. for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
  231. info = & flash_info[i];
  232. if (info->start[0] <= base && base < info->start[0] + info->size)
  233. break;
  234. }
  235. return i == CFG_MAX_FLASH_BANKS ? 0 : info;
  236. }
  237. /*-----------------------------------------------------------------------
  238. */
  239. void flash_print_info (flash_info_t *info)
  240. {
  241. int i;
  242. uchar *boottype;
  243. uchar *bootletter;
  244. char *fmt;
  245. uchar botbootletter[] = "B";
  246. uchar topbootletter[] = "T";
  247. uchar botboottype[] = "bottom boot sector";
  248. uchar topboottype[] = "top boot sector";
  249. if (info->flash_id == FLASH_UNKNOWN) {
  250. printf ("missing or unknown FLASH type\n");
  251. return;
  252. }
  253. switch (info->flash_id & FLASH_VENDMASK) {
  254. case FLASH_MAN_AMD: printf ("AMD "); break;
  255. case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
  256. case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  257. case FLASH_MAN_SST: printf ("SST "); break;
  258. case FLASH_MAN_STM: printf ("STM "); break;
  259. case FLASH_MAN_INTEL: printf ("INTEL "); break;
  260. default: printf ("Unknown Vendor "); break;
  261. }
  262. /* check for top or bottom boot, if it applies */
  263. if (info->flash_id & FLASH_BTYPE) {
  264. boottype = botboottype;
  265. bootletter = botbootletter;
  266. }
  267. else {
  268. boottype = topboottype;
  269. bootletter = topbootletter;
  270. }
  271. switch (info->flash_id & FLASH_TYPEMASK) {
  272. case FLASH_AM160B:
  273. fmt = "29LV160B%s (16 Mbit, %s)\n";
  274. break;
  275. case FLASH_28F800C3B:
  276. case FLASH_28F800C3T:
  277. fmt = "28F800C3%s (8 Mbit, %s)\n";
  278. break;
  279. case FLASH_INTEL800B:
  280. case FLASH_INTEL800T:
  281. fmt = "28F800B3%s (8 Mbit, %s)\n";
  282. break;
  283. case FLASH_28F160C3B:
  284. case FLASH_28F160C3T:
  285. fmt = "28F160C3%s (16 Mbit, %s)\n";
  286. break;
  287. case FLASH_INTEL160B:
  288. case FLASH_INTEL160T:
  289. fmt = "28F160B3%s (16 Mbit, %s)\n";
  290. break;
  291. case FLASH_28F320C3B:
  292. case FLASH_28F320C3T:
  293. fmt = "28F320C3%s (32 Mbit, %s)\n";
  294. break;
  295. case FLASH_INTEL320B:
  296. case FLASH_INTEL320T:
  297. fmt = "28F320B3%s (32 Mbit, %s)\n";
  298. break;
  299. case FLASH_28F640C3B:
  300. case FLASH_28F640C3T:
  301. fmt = "28F640C3%s (64 Mbit, %s)\n";
  302. break;
  303. case FLASH_INTEL640B:
  304. case FLASH_INTEL640T:
  305. fmt = "28F640B3%s (64 Mbit, %s)\n";
  306. break;
  307. default:
  308. fmt = "Unknown Chip Type\n";
  309. break;
  310. }
  311. printf (fmt, bootletter, boottype);
  312. printf (" Size: %ld MB in %d Sectors\n",
  313. info->size >> 20,
  314. info->sector_count);
  315. printf (" Sector Start Addresses:");
  316. for (i=0; i<info->sector_count; ++i) {
  317. if ((i % 5) == 0) {
  318. printf ("\n ");
  319. }
  320. printf (" %08lX%s", info->start[i],
  321. info->protect[i] ? " (RO)" : " ");
  322. }
  323. printf ("\n");
  324. }
  325. /*-----------------------------------------------------------------------
  326. */
  327. /*
  328. * The following code cannot be run from FLASH!
  329. */
  330. ulong flash_get_size (FPWV *addr, flash_info_t *info)
  331. {
  332. FUNCPTR_RD absEntry;
  333. FPW retValue;
  334. int flag;
  335. load_cmd(IN_RAM_CMD_READ);
  336. absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
  337. flag = disable_interrupts();
  338. absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
  339. if (flag) enable_interrupts();
  340. udelay(100);
  341. flag = disable_interrupts();
  342. absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue));
  343. absEntry(FLASH29_CMD_READ_RESET,0,0,0);
  344. if (flag) enable_interrupts();
  345. udelay(100);
  346. switch (retValue) {
  347. case (FPW)AMD_ID_LV160B:
  348. info->flash_id += FLASH_AM160B;
  349. info->sector_count = 35;
  350. info->size = 0x00400000;
  351. break; /* => 8 or 16 MB */
  352. default:
  353. info->flash_id = FLASH_UNKNOWN;
  354. info->sector_count = 0;
  355. info->size = 0;
  356. return (0); /* => no or unknown flash */
  357. }
  358. flash_get_offsets((ulong)addr, info);
  359. return (info->size);
  360. }
  361. /*-----------------------------------------------------------------------
  362. */
  363. int flash_erase (flash_info_t *info, int s_first, int s_last)
  364. {
  365. FPWV *addr;
  366. int flag, prot, sect;
  367. ulong start, now, last;
  368. int rcode = 0;
  369. FUNCPTR_WR absEntry;
  370. load_cmd(IN_RAM_CMD_WRITE);
  371. absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
  372. if ((s_first < 0) || (s_first > s_last)) {
  373. if (info->flash_id == FLASH_UNKNOWN) {
  374. printf ("- missing\n");
  375. } else {
  376. printf ("- no sectors to erase\n");
  377. }
  378. return 1;
  379. }
  380. switch (info->flash_id & FLASH_TYPEMASK) {
  381. case FLASH_AM160B:
  382. break;
  383. case FLASH_UNKNOWN:
  384. default:
  385. printf ("Can't erase unknown flash type %08lx - aborted\n",
  386. info->flash_id);
  387. return 1;
  388. }
  389. prot = 0;
  390. for (sect=s_first; sect<=s_last; ++sect) {
  391. if (info->protect[sect]) {
  392. prot++;
  393. }
  394. }
  395. if (prot) {
  396. printf ("- Warning: %d protected sectors will not be erased!\n",
  397. prot);
  398. } else {
  399. printf ("\n");
  400. }
  401. last = get_timer(0);
  402. /* Start erase on unprotected sectors */
  403. for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
  404. if (info->protect[sect] != 0) /* protected, skip it */
  405. continue;
  406. /* Disable interrupts which might cause a timeout here */
  407. flag = disable_interrupts();
  408. addr = (FPWV *)(info->start[sect]);
  409. absEntry(FLASH29_CMD_SECTOR, addr, 0);
  410. /* re-enable interrupts if necessary */
  411. if (flag)
  412. enable_interrupts();
  413. start = get_timer(0);
  414. while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) {
  415. /* show that we're waiting */
  416. if ((get_timer(last)) > CFG_HZ) {/* every second */
  417. putc ('.');
  418. last = get_timer(0);
  419. }
  420. }
  421. flag = disable_interrupts();
  422. absEntry(FLASH29_CMD_READ_RESET,0,0);
  423. if (flag)
  424. enable_interrupts();
  425. }
  426. printf (" done\n");
  427. return rcode;
  428. }
  429. /*-----------------------------------------------------------------------
  430. * Copy memory to flash, returns:
  431. * 0 - OK
  432. * 1 - write timeout
  433. * 2 - Flash not erased
  434. */
  435. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  436. {
  437. FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
  438. int bytes; /* number of bytes to program in current word */
  439. int left; /* number of bytes left to program */
  440. int i, res;
  441. for (left = cnt, res = 0;
  442. left > 0 && res == 0;
  443. addr += sizeof(data), left -= sizeof(data) - bytes) {
  444. bytes = addr & (sizeof(data) - 1);
  445. addr &= ~(sizeof(data) - 1);
  446. /* combine source and destination data so can program
  447. * an entire word of 16 or 32 bits
  448. */
  449. for (i = 0; i < sizeof(data); i++) {
  450. data <<= 8;
  451. if (i < bytes || i - bytes >= left )
  452. data += *((uchar *)addr + i);
  453. else
  454. data += *src++;
  455. }
  456. res = write_word(info, (FPWV *)addr, data);
  457. }
  458. return (res);
  459. }
  460. static int write_word (flash_info_t *info, FPWV *dest, FPW data)
  461. {
  462. int res = 0; /* result, assume success */
  463. FUNCPTR_WR absEntry;
  464. int flag;
  465. /* Check if Flash is (sufficiently) erased */
  466. if ((*dest & data) != data) {
  467. return (2);
  468. }
  469. if (info->start[0] != PHYS_FLASH_1)
  470. {
  471. return (3);
  472. }
  473. load_cmd(IN_RAM_CMD_WRITE);
  474. absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
  475. flag = disable_interrupts();
  476. absEntry(FLASH29_CMD_PROGRAM,dest,data);
  477. if (flag) enable_interrupts();
  478. udelay(100);
  479. flag = disable_interrupts();
  480. absEntry(FLASH29_CMD_READ_RESET,0,0);
  481. if (flag) enable_interrupts();
  482. return (res);
  483. }