hcu5.c 15 KB

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  1. /*
  2. *(C) Copyright 2005-2008 Netstal Maschinen AG
  3. * Niklaus Giger (Niklaus.Giger@netstal.com)
  4. *
  5. * This source code is free software; you can redistribute it
  6. * and/or modify it in source code form under the terms of the GNU
  7. * General Public License as published by the Free Software
  8. * Foundation; either version 2 of the License, or (at your option)
  9. * any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  19. */
  20. #include <common.h>
  21. #include <asm/processor.h>
  22. #include <ppc440.h>
  23. #include <asm/io.h>
  24. #include "../common/nm.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  27. #undef BOOTSTRAP_OPTION_A_ACTIVE
  28. #define SDR0_CP440 0x0180
  29. #define SYSTEM_RESET 0x30000000
  30. #define CHIP_RESET 0x20000000
  31. #define SDR0_ECID0 0x0080
  32. #define SDR0_ECID1 0x0081
  33. #define SDR0_ECID2 0x0082
  34. #define SDR0_ECID3 0x0083
  35. #define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
  36. #define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
  37. #define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000)
  38. #define HCU_SW_INSTALL_REQUESTED 0x10
  39. /*
  40. * This function is run very early, out of flash, and before devices are
  41. * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
  42. * of being in the init_sequence array.
  43. *
  44. * The SDRAM has been initialized already -- start.S:start called
  45. * init.S:init_sdram early on -- but it is not yet being used for
  46. * anything, not even stack. So be careful.
  47. */
  48. int board_early_init_f(void)
  49. {
  50. #ifdef BOOTSTRAP_OPTION_A_ACTIVE
  51. /* Booting with Bootstrap Option A
  52. * First boot, with CPR0_ICFG_RLI_MASK == 0
  53. * no we setup varios boot strapping register,
  54. * then we do reset the PPC440 using a chip reset
  55. * Unfortunately, we cannot use this option, as Nto1 is not set
  56. * with Bootstrap Option A and cannot be changed later on by SW
  57. * There are no other possible boostrap options with a 8 bit ROM
  58. * See Errata (Version 1.04) CHIP_9
  59. */
  60. u32 cpr0icfg;
  61. u32 dbcr;
  62. mfcpr(CPR0_ICFG, cpr0icfg);
  63. if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
  64. mtcpr(CPR0_MALD, 0x02000000);
  65. mtcpr(CPR0_OPBD, 0x02000000);
  66. mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
  67. mtcpr(CPR0_PLLC, 0x40000238);
  68. mtcpr(CPR0_PLLD, 0x01010414);
  69. mtcpr(CPR0_PRIMAD, 0x01000000);
  70. mtcpr(CPR0_PRIMBD, 0x01000000);
  71. mtcpr(CPR0_SPCID, 0x03000000);
  72. mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
  73. mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
  74. mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
  75. /*
  76. * Initiate system reset in debug control register DBCR
  77. */
  78. dbcr = mfspr(dbcr0);
  79. mtspr(dbcr0, dbcr | CHIP_RESET);
  80. }
  81. mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
  82. #endif
  83. mtdcr(ebccfga, xbcfg);
  84. mtdcr(ebccfgd, 0xb8400000);
  85. /*
  86. * Setup the GPIO pins
  87. */
  88. out32(GPIO0_OR, 0x00000000);
  89. out32(GPIO0_TCR, 0x7C2FF1CF);
  90. out32(GPIO0_OSRL, 0x40055000);
  91. out32(GPIO0_OSRH, 0x00000000);
  92. out32(GPIO0_TSRL, 0x40055000);
  93. out32(GPIO0_TSRH, 0x00000400);
  94. out32(GPIO0_ISR1L, 0x40000000);
  95. out32(GPIO0_ISR1H, 0x00000000);
  96. out32(GPIO0_ISR2L, 0x00000000);
  97. out32(GPIO0_ISR2H, 0x00000000);
  98. out32(GPIO0_ISR3L, 0x00000000);
  99. out32(GPIO0_ISR3H, 0x00000000);
  100. out32(GPIO1_OR, 0x00000000);
  101. out32(GPIO1_TCR, 0xC6007FFF);
  102. out32(GPIO1_OSRL, 0x00140000);
  103. out32(GPIO1_OSRH, 0x00000000);
  104. out32(GPIO1_TSRL, 0x00000000);
  105. out32(GPIO1_TSRH, 0x00000000);
  106. out32(GPIO1_ISR1L, 0x05415555);
  107. out32(GPIO1_ISR1H, 0x40000000);
  108. out32(GPIO1_ISR2L, 0x00000000);
  109. out32(GPIO1_ISR2H, 0x00000000);
  110. out32(GPIO1_ISR3L, 0x00000000);
  111. out32(GPIO1_ISR3H, 0x00000000);
  112. /*
  113. * Setup the interrupt controller polarities, triggers, etc.
  114. */
  115. mtdcr(uic0sr, 0xffffffff); /* clear all */
  116. mtdcr(uic0er, 0x00000000); /* disable all */
  117. mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
  118. mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
  119. mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
  120. mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
  121. mtdcr(uic0sr, 0xffffffff); /* clear all */
  122. mtdcr(uic1sr, 0xffffffff); /* clear all */
  123. mtdcr(uic1er, 0x00000000); /* disable all */
  124. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  125. mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
  126. mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
  127. mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
  128. mtdcr(uic1sr, 0xffffffff); /* clear all */
  129. mtdcr(uic2sr, 0xffffffff); /* clear all */
  130. mtdcr(uic2er, 0x00000000); /* disable all */
  131. mtdcr(uic2cr, 0x00000000); /* all non-critical */
  132. mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
  133. mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
  134. mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
  135. mtdcr(uic2sr, 0xffffffff); /* clear all */
  136. mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
  137. mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
  138. /* setup BOOT FLASH */
  139. mtsdr(SDR0_CUST0, 0xC0082350);
  140. return 0;
  141. }
  142. #ifdef CONFIG_BOARD_PRE_INIT
  143. int board_pre_init(void)
  144. {
  145. return board_early_init_f();
  146. }
  147. #endif
  148. int sys_install_requested(void)
  149. {
  150. u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
  151. return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
  152. }
  153. int checkboard(void)
  154. {
  155. u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
  156. u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
  157. u16 generation = in_be16(boardVersReg) & 0xf0;
  158. u16 index = in_be16(boardVersReg) & 0x0f;
  159. u32 ecid0, ecid1, ecid2, ecid3;
  160. nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
  161. mfsdr(SDR0_ECID0, ecid0);
  162. mfsdr(SDR0_ECID1, ecid1);
  163. mfsdr(SDR0_ECID2, ecid2);
  164. mfsdr(SDR0_ECID3, ecid3);
  165. printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
  166. return 0;
  167. }
  168. u32 hcu_led_get(void)
  169. {
  170. return in16(SYS_IO_ADDRESS) & 0x3f;
  171. }
  172. /*
  173. * hcu_led_set value to be placed into the LEDs (max 6 bit)
  174. */
  175. void hcu_led_set(u32 value)
  176. {
  177. out16(SYS_IO_ADDRESS, value);
  178. }
  179. /*
  180. * get_serial_number
  181. */
  182. u32 get_serial_number(void)
  183. {
  184. u32 *serial = (u32 *)CFG_FLASH_BASE;
  185. if (in_be32(serial) == 0xffffffff)
  186. return 0;
  187. return in_be32(serial);
  188. }
  189. /*
  190. * hcu_get_slot
  191. */
  192. u32 hcu_get_slot(void)
  193. {
  194. u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
  195. return in_be16(slot) & 0x7f;
  196. }
  197. /*
  198. * misc_init_r.
  199. */
  200. int misc_init_r(void)
  201. {
  202. unsigned long usb2d0cr = 0;
  203. unsigned long usb2phy0cr, usb2h0cr = 0;
  204. unsigned long sdr0_pfc1;
  205. #ifdef CONFIG_ENV_IS_IN_FLASH
  206. /* Monitor protection ON by default */
  207. (void)flash_protect(FLAG_PROTECT_SET,
  208. -CFG_MONITOR_LEN,
  209. 0xffffffff,
  210. &flash_info[0]);
  211. #ifdef CFG_ENV_ADDR_REDUND
  212. /* Env protection ON by default */
  213. (void)flash_protect(FLAG_PROTECT_SET,
  214. CFG_ENV_ADDR_REDUND,
  215. CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
  216. &flash_info[0]);
  217. #endif
  218. #endif
  219. /*
  220. * USB stuff...
  221. */
  222. /* SDR Setting */
  223. mfsdr(SDR0_PFC1, sdr0_pfc1);
  224. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  225. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  226. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  227. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  228. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
  229. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  230. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
  231. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  232. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
  233. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  234. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
  235. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  236. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
  237. /* An 8-bit/60MHz interface is the only possible alternative
  238. * when connecting the Device to the PHY
  239. */
  240. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  241. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
  242. /* To enable the USB 2.0 Device function through the UTMI interface */
  243. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  244. usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
  245. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  246. sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
  247. mtsdr(SDR0_PFC1, sdr0_pfc1);
  248. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  249. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  250. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  251. /*clear resets*/
  252. udelay(1000);
  253. mtsdr(SDR0_SRST1, 0x00000000);
  254. udelay(1000);
  255. mtsdr(SDR0_SRST0, 0x00000000);
  256. printf("USB: Host(int phy) Device(ext phy)\n");
  257. common_misc_init_r();
  258. set_params_for_sw_install( sys_install_requested(), "hcu5" );
  259. /* We cannot easily enable trace before, as there are other
  260. * routines messing around with sdr0_pfc1. And I do not need it.
  261. */
  262. if (mfspr(dbcr0) & 0x80000000) {
  263. /* External debugger alive
  264. * enable trace facilty for Lauterbach
  265. * CCR0[DTB]=0 Enable broadcast of trace information
  266. * SDR0_PFC0[TRE] Trace signals are enabled instead of
  267. * GPIO49-63
  268. */
  269. mtspr(ccr0, mfspr(ccr0) &~ (CCR0_DTB));
  270. mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
  271. }
  272. return 0;
  273. }
  274. #ifdef CONFIG_PCI
  275. int board_with_pci(void)
  276. {
  277. u32 reg;
  278. mfsdr(sdr_pci0, reg);
  279. return (reg & SDR0_XCR_PAE_MASK);
  280. }
  281. /*
  282. * pci_pre_init
  283. *
  284. * This routine is called just prior to registering the hose and gives
  285. * the board the opportunity to check things. Returning a value of zero
  286. * indicates that things are bad & PCI initialization should be aborted.
  287. *
  288. * Different boards may wish to customize the pci controller structure
  289. * (add regions, override default access routines, etc) or perform
  290. * certain pre-initialization actions.
  291. *
  292. */
  293. int pci_pre_init(struct pci_controller *hose)
  294. {
  295. unsigned long addr;
  296. if (!board_with_pci()) { return 0; }
  297. /*
  298. * Set priority for all PLB3 devices to 0.
  299. * Set PLB3 arbiter to fair mode.
  300. */
  301. mfsdr(sdr_amp1, addr);
  302. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  303. addr = mfdcr(plb3_acr);
  304. mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
  305. /*
  306. * Set priority for all PLB4 devices to 0.
  307. */
  308. mfsdr(sdr_amp0, addr);
  309. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  310. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  311. mtdcr(plb4_acr, addr); /* Sequoia */
  312. /*
  313. * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
  314. * Workaround: Disable write pipelining to DDR SDRAM by setting
  315. * PLB0_ACR[WRP] = 0.
  316. */
  317. mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
  318. /* Segment1 */
  319. mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
  320. return board_with_pci();
  321. }
  322. /*
  323. * pci_target_init
  324. *
  325. * The bootstrap configuration provides default settings for the pci
  326. * inbound map (PIM). But the bootstrap config choices are limited and
  327. * may not be sufficient for a given board.
  328. *
  329. */
  330. void pci_target_init(struct pci_controller *hose)
  331. {
  332. if (!board_with_pci()) { return; }
  333. /*
  334. * Set up Direct MMIO registers
  335. *
  336. * PowerPC440EPX PCI Master configuration.
  337. * Map one 1Gig range of PLB/processor addresses to PCI memory space.
  338. * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
  339. * 0xA0000000-0xDFFFFFFF
  340. * Use byte reversed out routines to handle endianess.
  341. * Make this region non-prefetchable.
  342. */
  343. /* PMM0 Mask/Attribute - disabled b4 setting */
  344. out32r(PCIX0_PMM0MA, 0x00000000);
  345. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  346. /* PMM0 PCI Low Address */
  347. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
  348. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  349. /* 512M + No prefetching, and enable region */
  350. out32r(PCIX0_PMM0MA, 0xE0000001);
  351. /* PMM0 Mask/Attribute - disabled b4 setting */
  352. out32r(PCIX0_PMM1MA, 0x00000000);
  353. out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  354. /* PMM0 PCI Low Address */
  355. out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
  356. out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
  357. /* 512M + No prefetching, and enable region */
  358. out32r(PCIX0_PMM1MA, 0xE0000001);
  359. out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  360. out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
  361. out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
  362. out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
  363. /*
  364. * Set up Configuration registers
  365. */
  366. /* Program the board's subsystem id/vendor id */
  367. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  368. CFG_PCI_SUBSYS_VENDORID);
  369. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
  370. /* Configure command register as bus master */
  371. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  372. /* 240nS PCI clock */
  373. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  374. /* No error reporting */
  375. pci_write_config_word(0, PCI_ERREN, 0);
  376. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  377. }
  378. /*
  379. * pci_master_init
  380. *
  381. */
  382. void pci_master_init(struct pci_controller *hose)
  383. {
  384. unsigned short temp_short;
  385. if (!board_with_pci()) { return; }
  386. /*---------------------------------------------------------------
  387. * Write the PowerPC440 EP PCI Configuration regs.
  388. * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  389. * Enable PowerPC440 EP to act as a PCI memory target (PTM).
  390. *--------------------------------------------------------------*/
  391. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  392. pci_write_config_word(0, PCI_COMMAND,
  393. temp_short | PCI_COMMAND_MASTER |
  394. PCI_COMMAND_MEMORY);
  395. }
  396. /*
  397. * is_pci_host
  398. *
  399. * This routine is called to determine if a pci scan should be
  400. * performed. With various hardware environments (especially cPCI and
  401. * PPMC) it's insufficient to depend on the state of the arbiter enable
  402. * bit in the strap register, or generic host/adapter assumptions.
  403. *
  404. * Rather than hard-code a bad assumption in the general 440 code, the
  405. * 440 pci code requires the board to decide at runtime.
  406. *
  407. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  408. *
  409. */
  410. int is_pci_host(struct pci_controller *hose)
  411. {
  412. return 1;
  413. }
  414. #endif /* defined(CONFIG_PCI) */
  415. #if defined(CONFIG_POST)
  416. /*
  417. * Returns 1 if keys pressed to start the power-on long-running tests
  418. * Called from board_init_f().
  419. */
  420. int post_hotkeys_pressed(void)
  421. {
  422. return 0; /* No hotkeys supported */
  423. }
  424. #endif /* CONFIG_POST */
  425. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  426. void ft_board_setup(void *blob, bd_t *bd)
  427. {
  428. ft_cpu_setup(blob, bd);
  429. }
  430. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
  431. /*
  432. * Hardcoded flash setup:
  433. * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
  434. */
  435. ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
  436. {
  437. if (banknum == 0) { /* non-CFI boot flash */
  438. info->portwidth = 1;
  439. info->chipwidth = 1;
  440. info->interface = FLASH_CFI_X8;
  441. return 1;
  442. } else
  443. return 0;
  444. }