pmc440.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878
  1. /*
  2. * (C) Copyright 2007-2008
  3. * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  4. * Based on board/amcc/sequoia/sequoia.c
  5. *
  6. * (C) Copyright 2006
  7. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  8. *
  9. * (C) Copyright 2006
  10. * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11. * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <libfdt.h>
  30. #include <fdt_support.h>
  31. #include <ppc440.h>
  32. #include <asm/processor.h>
  33. #include <asm/io.h>
  34. #include <asm/bitops.h>
  35. #include <command.h>
  36. #include <i2c.h>
  37. #ifdef CONFIG_RESET_PHY_R
  38. #include <miiphy.h>
  39. #endif
  40. #include <serial.h>
  41. #include "fpga.h"
  42. #include "pmc440.h"
  43. DECLARE_GLOBAL_DATA_PTR;
  44. extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  45. ulong flash_get_size(ulong base, int banknum);
  46. int pci_is_66mhz(void);
  47. int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  48. uchar *buffer, unsigned cnt);
  49. struct serial_device *default_serial_console(void)
  50. {
  51. uchar buf[4];
  52. ulong delay;
  53. int i;
  54. ulong val;
  55. /*
  56. * Use default console on P4 when strapping jumper
  57. * is installed (bootstrap option != 'H').
  58. */
  59. mfsdr(SDR_PINSTP, val);
  60. if (((val & 0xf0000000) >> 29) != 7)
  61. return &serial1_device;
  62. ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
  63. if (!(scratchreg & 0x80)) {
  64. /* mark scratchreg valid */
  65. scratchreg = (scratchreg & 0xffffff00) | 0x80;
  66. i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR,
  67. 0x10, buf, 4);
  68. if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
  69. scratchreg |= buf[2];
  70. /* bringup delay for console */
  71. for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
  72. udelay(1000);
  73. }
  74. } else
  75. scratchreg |= 0x01;
  76. out_be32((void*)GPIO0_ISR3L, scratchreg);
  77. }
  78. if (scratchreg & 0x01)
  79. return &serial1_device;
  80. else
  81. return &serial0_device;
  82. }
  83. int board_early_init_f(void)
  84. {
  85. u32 sdr0_cust0;
  86. u32 sdr0_pfc1, sdr0_pfc2;
  87. u32 reg;
  88. /* general EBC configuration (disable EBC timeouts) */
  89. mtdcr(ebccfga, xbcfg);
  90. mtdcr(ebccfgd, 0xf8400000);
  91. /*
  92. * Setup the GPIO pins
  93. * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
  94. */
  95. out32(GPIO0_OR, 0x40000002);
  96. out32(GPIO0_TCR, 0x4c90011f);
  97. out32(GPIO0_OSRL, 0x28011400);
  98. out32(GPIO0_OSRH, 0x55005000);
  99. out32(GPIO0_TSRL, 0x08011400);
  100. out32(GPIO0_TSRH, 0x55005000);
  101. out32(GPIO0_ISR1L, 0x54000000);
  102. out32(GPIO0_ISR1H, 0x00000000);
  103. out32(GPIO0_ISR2L, 0x44000000);
  104. out32(GPIO0_ISR2H, 0x00000100);
  105. out32(GPIO0_ISR3L, 0x00000000);
  106. out32(GPIO0_ISR3H, 0x00000000);
  107. out32(GPIO1_OR, 0x80002408);
  108. out32(GPIO1_TCR, 0xd6003c08);
  109. out32(GPIO1_OSRL, 0x0a5a0000);
  110. out32(GPIO1_OSRH, 0x00000000);
  111. out32(GPIO1_TSRL, 0x00000000);
  112. out32(GPIO1_TSRH, 0x00000000);
  113. out32(GPIO1_ISR1L, 0x00005555);
  114. out32(GPIO1_ISR1H, 0x40000000);
  115. out32(GPIO1_ISR2L, 0x04010000);
  116. out32(GPIO1_ISR2H, 0x00000000);
  117. out32(GPIO1_ISR3L, 0x01400000);
  118. out32(GPIO1_ISR3H, 0x00000000);
  119. /* patch PLB:PCI divider for 66MHz PCI */
  120. mfcpr(clk_spcid, reg);
  121. if (pci_is_66mhz() && (reg != 0x02000000)) {
  122. mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
  123. mfcpr(clk_icfg, reg);
  124. reg |= CPR0_ICFG_RLI_MASK;
  125. mtcpr(clk_icfg, reg);
  126. mtspr(dbcr0, 0x20000000); /* do chip reset */
  127. }
  128. /*
  129. * Setup the interrupt controller polarities, triggers, etc.
  130. */
  131. mtdcr(uic0sr, 0xffffffff); /* clear all */
  132. mtdcr(uic0er, 0x00000000); /* disable all */
  133. mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
  134. mtdcr(uic0pr, 0xfffff7ef);
  135. mtdcr(uic0tr, 0x00000000);
  136. mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
  137. mtdcr(uic0sr, 0xffffffff); /* clear all */
  138. mtdcr(uic1sr, 0xffffffff); /* clear all */
  139. mtdcr(uic1er, 0x00000000); /* disable all */
  140. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  141. mtdcr(uic1pr, 0xffffc7f5);
  142. mtdcr(uic1tr, 0x00000000);
  143. mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
  144. mtdcr(uic1sr, 0xffffffff); /* clear all */
  145. mtdcr(uic2sr, 0xffffffff); /* clear all */
  146. mtdcr(uic2er, 0x00000000); /* disable all */
  147. mtdcr(uic2cr, 0x00000000); /* all non-critical */
  148. mtdcr(uic2pr, 0x27ffffff);
  149. mtdcr(uic2tr, 0x00000000);
  150. mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
  151. mtdcr(uic2sr, 0xffffffff); /* clear all */
  152. /* select Ethernet pins */
  153. mfsdr(SDR0_PFC1, sdr0_pfc1);
  154. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
  155. SDR0_PFC1_SELECT_CONFIG_4;
  156. mfsdr(SDR0_PFC2, sdr0_pfc2);
  157. sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
  158. SDR0_PFC2_SELECT_CONFIG_4;
  159. /* enable 2nd IIC */
  160. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
  161. mtsdr(SDR0_PFC2, sdr0_pfc2);
  162. mtsdr(SDR0_PFC1, sdr0_pfc1);
  163. /* setup NAND FLASH */
  164. mfsdr(SDR0_CUST0, sdr0_cust0);
  165. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  166. SDR0_CUST0_NDFC_ENABLE |
  167. SDR0_CUST0_NDFC_BW_8_BIT |
  168. SDR0_CUST0_NDFC_ARE_MASK |
  169. (0x80000000 >> (28 + CFG_NAND_CS));
  170. mtsdr(SDR0_CUST0, sdr0_cust0);
  171. return 0;
  172. }
  173. /*
  174. * misc_init_r.
  175. */
  176. int misc_init_r(void)
  177. {
  178. uint pbcr;
  179. int size_val = 0;
  180. u32 reg;
  181. unsigned long usb2d0cr = 0;
  182. unsigned long usb2phy0cr, usb2h0cr = 0;
  183. unsigned long sdr0_pfc1;
  184. char *act = getenv("usbact");
  185. /*
  186. * FLASH stuff...
  187. */
  188. /* Re-do sizing to get full correct info */
  189. /* adjust flash start and offset */
  190. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  191. gd->bd->bi_flashoffset = 0;
  192. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  193. mtdcr(ebccfga, pb2cr);
  194. #else
  195. mtdcr(ebccfga, pb0cr);
  196. #endif
  197. pbcr = mfdcr(ebccfgd);
  198. size_val = ffs(gd->bd->bi_flashsize) - 21;
  199. pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
  200. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  201. mtdcr(ebccfga, pb2cr);
  202. #else
  203. mtdcr(ebccfga, pb0cr);
  204. #endif
  205. mtdcr(ebccfgd, pbcr);
  206. /*
  207. * Re-check to get correct base address
  208. */
  209. flash_get_size(gd->bd->bi_flashstart, 0);
  210. #ifdef CONFIG_ENV_IS_IN_FLASH
  211. /* Monitor protection ON by default */
  212. (void)flash_protect(FLAG_PROTECT_SET,
  213. -CFG_MONITOR_LEN,
  214. 0xffffffff,
  215. &flash_info[0]);
  216. /* Env protection ON by default */
  217. (void)flash_protect(FLAG_PROTECT_SET,
  218. CFG_ENV_ADDR_REDUND,
  219. CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
  220. &flash_info[0]);
  221. #endif
  222. /*
  223. * USB suff...
  224. */
  225. if ((act == NULL || strcmp(act, "hostdev") == 0) &&
  226. !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
  227. /* SDR Setting */
  228. mfsdr(SDR0_PFC1, sdr0_pfc1);
  229. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  230. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  231. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  232. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  233. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  234. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  235. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
  236. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  237. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
  238. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  239. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
  240. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  241. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
  242. /*
  243. * An 8-bit/60MHz interface is the only possible alternative
  244. * when connecting the Device to the PHY
  245. */
  246. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  247. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
  248. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  249. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  250. mtsdr(SDR0_PFC1, sdr0_pfc1);
  251. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  252. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  253. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  254. /* clear resets */
  255. udelay(1000);
  256. mtsdr(SDR0_SRST1, 0x00000000);
  257. udelay(1000);
  258. mtsdr(SDR0_SRST0, 0x00000000);
  259. printf("USB: Host\n");
  260. } else if ((strcmp(act, "dev") == 0) ||
  261. (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
  262. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  263. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  264. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  265. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  266. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
  267. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  268. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
  269. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  270. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
  271. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  272. udelay (1000);
  273. mtsdr(SDR0_SRST1, 0x672c6000);
  274. udelay (1000);
  275. mtsdr(SDR0_SRST0, 0x00000080);
  276. udelay (1000);
  277. mtsdr(SDR0_SRST1, 0x60206000);
  278. *(unsigned int *)(0xe0000350) = 0x00000001;
  279. udelay (1000);
  280. mtsdr(SDR0_SRST1, 0x60306000);
  281. /* SDR Setting */
  282. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  283. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  284. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  285. mfsdr(SDR0_PFC1, sdr0_pfc1);
  286. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  287. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  288. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  289. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
  290. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  291. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
  292. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  293. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
  294. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  295. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
  296. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  297. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
  298. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  299. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  300. sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
  301. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  302. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  303. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  304. mtsdr(SDR0_PFC1, sdr0_pfc1);
  305. /*clear resets*/
  306. udelay(1000);
  307. mtsdr(SDR0_SRST1, 0x00000000);
  308. udelay(1000);
  309. mtsdr(SDR0_SRST0, 0x00000000);
  310. printf("USB: Device\n");
  311. }
  312. /*
  313. * Clear PLB4A0_ACR[WRP]
  314. * This fix will make the MAL burst disabling patch for the Linux
  315. * EMAC driver obsolete.
  316. */
  317. reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
  318. mtdcr(plb4_acr, reg);
  319. #ifdef CONFIG_FPGA
  320. pmc440_init_fpga();
  321. #endif
  322. /* turn off POST LED */
  323. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
  324. /* turn on RUN LED */
  325. out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
  326. return 0;
  327. }
  328. int is_monarch(void)
  329. {
  330. if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
  331. return 0;
  332. return 1;
  333. }
  334. int pci_is_66mhz(void)
  335. {
  336. if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
  337. return 1;
  338. return 0;
  339. }
  340. int board_revision(void)
  341. {
  342. return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
  343. }
  344. int checkboard(void)
  345. {
  346. puts("Board: esd GmbH - PMC440");
  347. gd->board_type = board_revision();
  348. printf(", Rev 1.%ld, ", gd->board_type);
  349. if (!is_monarch()) {
  350. puts("non-");
  351. }
  352. printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
  353. return (0);
  354. }
  355. #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
  356. /*
  357. * Assign interrupts to PCI devices. Some OSs rely on this.
  358. */
  359. void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
  360. {
  361. unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
  362. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  363. int_line[PCI_DEV(dev) & 0x03]);
  364. }
  365. #endif
  366. /*
  367. * pci_pre_init
  368. *
  369. * This routine is called just prior to registering the hose and gives
  370. * the board the opportunity to check things. Returning a value of zero
  371. * indicates that things are bad & PCI initialization should be aborted.
  372. *
  373. * Different boards may wish to customize the pci controller structure
  374. * (add regions, override default access routines, etc) or perform
  375. * certain pre-initialization actions.
  376. */
  377. #if defined(CONFIG_PCI)
  378. int pci_pre_init(struct pci_controller *hose)
  379. {
  380. unsigned long addr;
  381. /*
  382. * Set priority for all PLB3 devices to 0.
  383. * Set PLB3 arbiter to fair mode.
  384. */
  385. mfsdr(sdr_amp1, addr);
  386. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  387. addr = mfdcr(plb3_acr);
  388. mtdcr(plb3_acr, addr | 0x80000000);
  389. /*
  390. * Set priority for all PLB4 devices to 0.
  391. */
  392. mfsdr(sdr_amp0, addr);
  393. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  394. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  395. mtdcr(plb4_acr, addr);
  396. /*
  397. * Set Nebula PLB4 arbiter to fair mode.
  398. */
  399. /* Segment0 */
  400. addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
  401. addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
  402. addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
  403. addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
  404. mtdcr(plb0_acr, addr);
  405. /* Segment1 */
  406. addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
  407. addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
  408. addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
  409. addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
  410. mtdcr(plb1_acr, addr);
  411. #ifdef CONFIG_PCI_PNP
  412. hose->fixup_irq = pmc440_pci_fixup_irq;
  413. #endif
  414. return 1;
  415. }
  416. #endif /* defined(CONFIG_PCI) */
  417. /*
  418. * pci_target_init
  419. *
  420. * The bootstrap configuration provides default settings for the pci
  421. * inbound map (PIM). But the bootstrap config choices are limited and
  422. * may not be sufficient for a given board.
  423. */
  424. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  425. void pci_target_init(struct pci_controller *hose)
  426. {
  427. char *ptmla_str, *ptmms_str;
  428. /*
  429. * Set up Direct MMIO registers
  430. */
  431. /*
  432. * PowerPC440EPX PCI Master configuration.
  433. * Map one 1Gig range of PLB/processor addresses to PCI memory space.
  434. * PLB address 0x80000000-0xBFFFFFFF
  435. * ==> PCI address 0x80000000-0xBFFFFFFF
  436. * Use byte reversed out routines to handle endianess.
  437. * Make this region non-prefetchable.
  438. */
  439. out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
  440. /* - disabled b4 setting */
  441. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  442. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
  443. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  444. out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
  445. /* and enable region */
  446. if (!is_monarch()) {
  447. ptmla_str = getenv("ptm1la");
  448. ptmms_str = getenv("ptm1ms");
  449. if(NULL != ptmla_str && NULL != ptmms_str ) {
  450. out32r(PCIX0_PTM1MS,
  451. simple_strtoul(ptmms_str, NULL, 16));
  452. out32r(PCIX0_PTM1LA,
  453. simple_strtoul(ptmla_str, NULL, 16));
  454. } else {
  455. /* BAR1: default top 64MB of RAM */
  456. out32r(PCIX0_PTM1MS, 0xfc000001);
  457. out32r(PCIX0_PTM1LA, 0x0c000000);
  458. }
  459. } else {
  460. /* BAR1: default: complete 256MB RAM */
  461. out32r(PCIX0_PTM1MS, 0xf0000001);
  462. out32r(PCIX0_PTM1LA, 0x00000000);
  463. }
  464. ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
  465. ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
  466. if(NULL != ptmla_str && NULL != ptmms_str ) {
  467. out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
  468. out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
  469. } else {
  470. /* BAR2: default: 16 MB FPGA + registers */
  471. out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
  472. out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
  473. }
  474. if (is_monarch()) {
  475. /* BAR2: map FPGA registers behind system memory at 1GB */
  476. pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
  477. }
  478. /*
  479. * Set up Configuration registers
  480. */
  481. /* Program the board's vendor id */
  482. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  483. CFG_PCI_SUBSYS_VENDORID);
  484. /* disabled for PMC405 backward compatibility */
  485. /* Configure command register as bus master */
  486. /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
  487. /* 240nS PCI clock */
  488. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  489. /* No error reporting */
  490. pci_write_config_word(0, PCI_ERREN, 0);
  491. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  492. if (!is_monarch()) {
  493. /* Program the board's subsystem id/classcode */
  494. pci_write_config_word(0, PCI_SUBSYSTEM_ID,
  495. CFG_PCI_SUBSYS_ID_NONMONARCH);
  496. pci_write_config_word(0, PCI_CLASS_SUB_CODE,
  497. CFG_PCI_CLASSCODE_NONMONARCH);
  498. /* PCI configuration done: release ERREADY */
  499. out_be32((void*)GPIO1_OR,
  500. in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
  501. out_be32((void*)GPIO1_TCR,
  502. in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
  503. } else {
  504. /* Program the board's subsystem id/classcode */
  505. pci_write_config_word(0, PCI_SUBSYSTEM_ID,
  506. CFG_PCI_SUBSYS_ID_MONARCH);
  507. pci_write_config_word(0, PCI_CLASS_SUB_CODE,
  508. CFG_PCI_CLASSCODE_MONARCH);
  509. }
  510. }
  511. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  512. /*
  513. * pci_master_init
  514. */
  515. #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
  516. void pci_master_init(struct pci_controller *hose)
  517. {
  518. unsigned short temp_short;
  519. /*
  520. * Write the PowerPC440 EP PCI Configuration regs.
  521. * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  522. * Enable PowerPC440 EP to act as a PCI memory target (PTM).
  523. */
  524. if (is_monarch()) {
  525. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  526. pci_write_config_word(0, PCI_COMMAND,
  527. temp_short | PCI_COMMAND_MASTER |
  528. PCI_COMMAND_MEMORY);
  529. }
  530. }
  531. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
  532. static void wait_for_pci_ready(void)
  533. {
  534. int i;
  535. char *s = getenv("pcidelay");
  536. if (s) {
  537. int ms = simple_strtoul(s, NULL, 10);
  538. printf("PCI: Waiting for %d ms\n", ms);
  539. for (i=0; i<ms; i++)
  540. udelay(1000);
  541. }
  542. if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
  543. printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
  544. while (1) {
  545. if (ctrlc()) {
  546. puts("abort\n");
  547. break;
  548. }
  549. if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
  550. printf("done\n");
  551. break;
  552. }
  553. }
  554. }
  555. }
  556. /*
  557. * is_pci_host
  558. *
  559. * This routine is called to determine if a pci scan should be
  560. * performed. With various hardware environments (especially cPCI and
  561. * PPMC) it's insufficient to depend on the state of the arbiter enable
  562. * bit in the strap register, or generic host/adapter assumptions.
  563. *
  564. * Rather than hard-code a bad assumption in the general 440 code, the
  565. * 440 pci code requires the board to decide at runtime.
  566. *
  567. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  568. */
  569. #if defined(CONFIG_PCI)
  570. int is_pci_host(struct pci_controller *hose)
  571. {
  572. char *s = getenv("pciscan");
  573. if (s == NULL)
  574. if (is_monarch()) {
  575. wait_for_pci_ready();
  576. return 1;
  577. } else
  578. return 0;
  579. else if (!strcmp(s, "yes"))
  580. return 1;
  581. return 0;
  582. }
  583. #endif /* defined(CONFIG_PCI) */
  584. #if defined(CONFIG_POST)
  585. /*
  586. * Returns 1 if keys pressed to start the power-on long-running tests
  587. * Called from board_init_f().
  588. */
  589. int post_hotkeys_pressed(void)
  590. {
  591. return 0; /* No hotkeys supported */
  592. }
  593. #endif /* CONFIG_POST */
  594. #ifdef CONFIG_RESET_PHY_R
  595. void reset_phy(void)
  596. {
  597. if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
  598. miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
  599. miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
  600. miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
  601. miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
  602. }
  603. if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
  604. miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
  605. miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
  606. miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
  607. miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
  608. }
  609. }
  610. #endif
  611. #if defined(CFG_EEPROM_WREN)
  612. /*
  613. * Input: <dev_addr> I2C address of EEPROM device to enable.
  614. * <state> -1: deliver current state
  615. * 0: disable write
  616. * 1: enable write
  617. * Returns: -1: wrong device address
  618. * 0: dis-/en- able done
  619. * 0/1: current state if <state> was -1.
  620. */
  621. int eeprom_write_enable(unsigned dev_addr, int state)
  622. {
  623. if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
  624. (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
  625. return -1;
  626. } else {
  627. switch (state) {
  628. case 1:
  629. /* Enable write access, clear bit GPIO_SINT2. */
  630. out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
  631. state = 0;
  632. break;
  633. case 0:
  634. /* Disable write access, set bit GPIO_SINT2. */
  635. out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
  636. state = 0;
  637. break;
  638. default:
  639. /* Read current status back. */
  640. state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
  641. break;
  642. }
  643. }
  644. return state;
  645. }
  646. #endif /* #if defined(CFG_EEPROM_WREN) */
  647. #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
  648. int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
  649. uchar *buffer, unsigned cnt)
  650. {
  651. unsigned end = offset + cnt;
  652. unsigned blk_off;
  653. int rcode = 0;
  654. #if defined(CFG_EEPROM_WREN)
  655. eeprom_write_enable(dev_addr, 1);
  656. #endif
  657. /*
  658. * Write data until done or would cross a write page boundary.
  659. * We must write the address again when changing pages
  660. * because the address counter only increments within a page.
  661. */
  662. while (offset < end) {
  663. unsigned alen, len;
  664. unsigned maxlen;
  665. uchar addr[2];
  666. blk_off = offset & 0xFF; /* block offset */
  667. addr[0] = offset >> 8; /* block number */
  668. addr[1] = blk_off; /* block offset */
  669. alen = 2;
  670. addr[0] |= dev_addr; /* insert device address */
  671. len = end - offset;
  672. #define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
  673. #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
  674. maxlen = BOOT_EEPROM_PAGE_SIZE -
  675. BOOT_EEPROM_PAGE_OFFSET(blk_off);
  676. if (maxlen > I2C_RXTX_LEN)
  677. maxlen = I2C_RXTX_LEN;
  678. if (len > maxlen)
  679. len = maxlen;
  680. if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
  681. rcode = 1;
  682. buffer += len;
  683. offset += len;
  684. #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
  685. udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
  686. #endif
  687. }
  688. #if defined(CFG_EEPROM_WREN)
  689. eeprom_write_enable(dev_addr, 0);
  690. #endif
  691. return rcode;
  692. }
  693. int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
  694. uchar *buffer, unsigned cnt)
  695. {
  696. unsigned end = offset + cnt;
  697. unsigned blk_off;
  698. int rcode = 0;
  699. /*
  700. * Read data until done or would cross a page boundary.
  701. * We must write the address again when changing pages
  702. * because the next page may be in a different device.
  703. */
  704. while (offset < end) {
  705. unsigned alen, len;
  706. unsigned maxlen;
  707. uchar addr[2];
  708. blk_off = offset & 0xFF; /* block offset */
  709. addr[0] = offset >> 8; /* block number */
  710. addr[1] = blk_off; /* block offset */
  711. alen = 2;
  712. addr[0] |= dev_addr; /* insert device address */
  713. len = end - offset;
  714. maxlen = 0x100 - blk_off;
  715. if (maxlen > I2C_RXTX_LEN)
  716. maxlen = I2C_RXTX_LEN;
  717. if (len > maxlen)
  718. len = maxlen;
  719. if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
  720. rcode = 1;
  721. buffer += len;
  722. offset += len;
  723. }
  724. return rcode;
  725. }
  726. #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
  727. int usb_board_init(void)
  728. {
  729. char *act = getenv("usbact");
  730. int i;
  731. if ((act == NULL || strcmp(act, "hostdev") == 0) &&
  732. !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
  733. /* enable power on USB socket */
  734. out_be32((void*)GPIO1_OR,
  735. in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
  736. for (i=0; i<1000; i++)
  737. udelay(1000);
  738. return 0;
  739. }
  740. int usb_board_stop(void)
  741. {
  742. /* disable power on USB socket */
  743. out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
  744. return 0;
  745. }
  746. int usb_board_init_fail(void)
  747. {
  748. usb_board_stop();
  749. return 0;
  750. }
  751. #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */