flash.c 17 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  25. /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  26. * has nothing to do with the flash chip being 8-bit or 16-bit.
  27. */
  28. #ifdef CONFIG_FLASH_16BIT
  29. typedef unsigned short FLASH_PORT_WIDTH;
  30. typedef volatile unsigned short FLASH_PORT_WIDTHV;
  31. #define FLASH_ID_MASK 0xFFFF
  32. #else
  33. typedef unsigned long FLASH_PORT_WIDTH;
  34. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  35. #define FLASH_ID_MASK 0xFFFFFFFF
  36. #endif
  37. #define FPW FLASH_PORT_WIDTH
  38. #define FPWV FLASH_PORT_WIDTHV
  39. #define ORMASK(size) ((-size) & OR_AM_MSK)
  40. #define FLASH_CYCLE1 0x0555
  41. #define FLASH_CYCLE2 0x02aa
  42. /*-----------------------------------------------------------------------
  43. * Functions
  44. */
  45. static ulong flash_get_size(FPWV *addr, flash_info_t *info);
  46. static void flash_reset(flash_info_t *info);
  47. static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
  48. static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
  49. static void flash_get_offsets(ulong base, flash_info_t *info);
  50. static flash_info_t *flash_get_info(ulong base);
  51. /*-----------------------------------------------------------------------
  52. * flash_init()
  53. *
  54. * sets up flash_info and returns size of FLASH (bytes)
  55. */
  56. unsigned long flash_init (void)
  57. {
  58. unsigned long size = 0;
  59. int i;
  60. /* Init: no FLASHes known */
  61. for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
  62. #if 0
  63. ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
  64. #else
  65. ulong flashbase = CFG_FLASH_BASE;
  66. #endif
  67. memset(&flash_info[i], 0, sizeof(flash_info_t));
  68. flash_info[i].size =
  69. flash_get_size((FPW *)flashbase, &flash_info[i]);
  70. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  71. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
  72. i, flash_info[i].size);
  73. }
  74. size += flash_info[i].size;
  75. }
  76. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  77. /* monitor protection ON by default */
  78. flash_protect(FLAG_PROTECT_SET,
  79. CFG_MONITOR_BASE,
  80. CFG_MONITOR_BASE+monitor_flash_len-1,
  81. flash_get_info(CFG_MONITOR_BASE));
  82. #endif
  83. #ifdef CONFIG_ENV_IS_IN_FLASH
  84. /* ENV protection ON by default */
  85. flash_protect(FLAG_PROTECT_SET,
  86. CFG_ENV_ADDR,
  87. CFG_ENV_ADDR+CFG_ENV_SIZE-1,
  88. flash_get_info(CFG_ENV_ADDR));
  89. #endif
  90. return size ? size : 1;
  91. }
  92. /*-----------------------------------------------------------------------
  93. */
  94. static void flash_reset(flash_info_t *info)
  95. {
  96. FPWV *base = (FPWV *)(info->start[0]);
  97. /* Put FLASH back in read mode */
  98. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
  99. *base = (FPW)0x00FF00FF; /* Intel Read Mode */
  100. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
  101. *base = (FPW)0x00F000F0; /* AMD Read Mode */
  102. }
  103. /*-----------------------------------------------------------------------
  104. */
  105. static void flash_get_offsets (ulong base, flash_info_t *info)
  106. {
  107. int i;
  108. /* set up sector start address table */
  109. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
  110. && (info->flash_id & FLASH_BTYPE)) {
  111. int bootsect_size; /* number of bytes/boot sector */
  112. int sect_size; /* number of bytes/regular sector */
  113. bootsect_size = 0x00002000 * (sizeof(FPW)/2);
  114. sect_size = 0x00010000 * (sizeof(FPW)/2);
  115. /* set sector offsets for bottom boot block type */
  116. for (i = 0; i < 8; ++i) {
  117. info->start[i] = base + (i * bootsect_size);
  118. }
  119. for (i = 8; i < info->sector_count; i++) {
  120. info->start[i] = base + ((i - 7) * sect_size);
  121. }
  122. }
  123. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
  124. && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
  125. int sect_size; /* number of bytes/sector */
  126. sect_size = 0x00010000 * (sizeof(FPW)/2);
  127. /* set up sector start address table (uniform sector type) */
  128. for( i = 0; i < info->sector_count; i++ )
  129. info->start[i] = base + (i * sect_size);
  130. }
  131. }
  132. /*-----------------------------------------------------------------------
  133. */
  134. static flash_info_t *flash_get_info(ulong base)
  135. {
  136. int i;
  137. flash_info_t * info;
  138. for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
  139. info = & flash_info[i];
  140. if (info->start[0] <= base && base < info->start[0] + info->size)
  141. break;
  142. }
  143. return i == CFG_MAX_FLASH_BANKS ? 0 : info;
  144. }
  145. /*-----------------------------------------------------------------------
  146. */
  147. void flash_print_info (flash_info_t *info)
  148. {
  149. int i;
  150. uchar *boottype;
  151. uchar *bootletter;
  152. char *fmt;
  153. uchar botbootletter[] = "B";
  154. uchar topbootletter[] = "T";
  155. uchar botboottype[] = "bottom boot sector";
  156. uchar topboottype[] = "top boot sector";
  157. if (info->flash_id == FLASH_UNKNOWN) {
  158. printf ("missing or unknown FLASH type\n");
  159. return;
  160. }
  161. switch (info->flash_id & FLASH_VENDMASK) {
  162. case FLASH_MAN_AMD: printf ("AMD "); break;
  163. case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
  164. case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  165. case FLASH_MAN_SST: printf ("SST "); break;
  166. case FLASH_MAN_STM: printf ("STM "); break;
  167. case FLASH_MAN_INTEL: printf ("INTEL "); break;
  168. default: printf ("Unknown Vendor "); break;
  169. }
  170. /* check for top or bottom boot, if it applies */
  171. if (info->flash_id & FLASH_BTYPE) {
  172. boottype = botboottype;
  173. bootletter = botbootletter;
  174. }
  175. else {
  176. boottype = topboottype;
  177. bootletter = topbootletter;
  178. }
  179. switch (info->flash_id & FLASH_TYPEMASK) {
  180. case FLASH_AM640U:
  181. fmt = "29LV641D (64 Mbit, uniform sectors)\n";
  182. break;
  183. case FLASH_28F800C3B:
  184. case FLASH_28F800C3T:
  185. fmt = "28F800C3%s (8 Mbit, %s)\n";
  186. break;
  187. case FLASH_INTEL800B:
  188. case FLASH_INTEL800T:
  189. fmt = "28F800B3%s (8 Mbit, %s)\n";
  190. break;
  191. case FLASH_28F160C3B:
  192. case FLASH_28F160C3T:
  193. fmt = "28F160C3%s (16 Mbit, %s)\n";
  194. break;
  195. case FLASH_INTEL160B:
  196. case FLASH_INTEL160T:
  197. fmt = "28F160B3%s (16 Mbit, %s)\n";
  198. break;
  199. case FLASH_28F320C3B:
  200. case FLASH_28F320C3T:
  201. fmt = "28F320C3%s (32 Mbit, %s)\n";
  202. break;
  203. case FLASH_INTEL320B:
  204. case FLASH_INTEL320T:
  205. fmt = "28F320B3%s (32 Mbit, %s)\n";
  206. break;
  207. case FLASH_28F640C3B:
  208. case FLASH_28F640C3T:
  209. fmt = "28F640C3%s (64 Mbit, %s)\n";
  210. break;
  211. case FLASH_INTEL640B:
  212. case FLASH_INTEL640T:
  213. fmt = "28F640B3%s (64 Mbit, %s)\n";
  214. break;
  215. default:
  216. fmt = "Unknown Chip Type\n";
  217. break;
  218. }
  219. printf (fmt, bootletter, boottype);
  220. printf (" Size: %ld MB in %d Sectors\n",
  221. info->size >> 20,
  222. info->sector_count);
  223. printf (" Sector Start Addresses:");
  224. for (i=0; i<info->sector_count; ++i) {
  225. if ((i % 5) == 0) {
  226. printf ("\n ");
  227. }
  228. printf (" %08lX%s", info->start[i],
  229. info->protect[i] ? " (RO)" : " ");
  230. }
  231. printf ("\n");
  232. }
  233. /*-----------------------------------------------------------------------
  234. */
  235. /*
  236. * The following code cannot be run from FLASH!
  237. */
  238. ulong flash_get_size (FPWV *addr, flash_info_t *info)
  239. {
  240. /* Write auto select command: read Manufacturer ID */
  241. /* Write auto select command sequence and test FLASH answer */
  242. addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
  243. addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
  244. addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
  245. /* The manufacturer codes are only 1 byte, so just use 1 byte.
  246. * This works for any bus width and any FLASH device width.
  247. */
  248. udelay(100);
  249. switch (addr[0] & 0xff) {
  250. case (uchar)AMD_MANUFACT:
  251. info->flash_id = FLASH_MAN_AMD;
  252. break;
  253. case (uchar)INTEL_MANUFACT:
  254. info->flash_id = FLASH_MAN_INTEL;
  255. break;
  256. default:
  257. info->flash_id = FLASH_UNKNOWN;
  258. info->sector_count = 0;
  259. info->size = 0;
  260. break;
  261. }
  262. /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
  263. if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
  264. case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
  265. info->flash_id += FLASH_AM640U;
  266. info->sector_count = 128;
  267. info->size = 0x00800000 * (sizeof(FPW)/2);
  268. break; /* => 8 or 16 MB */
  269. case (FPW)INTEL_ID_28F800C3B:
  270. info->flash_id += FLASH_28F800C3B;
  271. info->sector_count = 23;
  272. info->size = 0x00100000 * (sizeof(FPW)/2);
  273. break; /* => 1 or 2 MB */
  274. case (FPW)INTEL_ID_28F800B3B:
  275. info->flash_id += FLASH_INTEL800B;
  276. info->sector_count = 23;
  277. info->size = 0x00100000 * (sizeof(FPW)/2);
  278. break; /* => 1 or 2 MB */
  279. case (FPW)INTEL_ID_28F160C3B:
  280. info->flash_id += FLASH_28F160C3B;
  281. info->sector_count = 39;
  282. info->size = 0x00200000 * (sizeof(FPW)/2);
  283. break; /* => 2 or 4 MB */
  284. case (FPW)INTEL_ID_28F160B3B:
  285. info->flash_id += FLASH_INTEL160B;
  286. info->sector_count = 39;
  287. info->size = 0x00200000 * (sizeof(FPW)/2);
  288. break; /* => 2 or 4 MB */
  289. case (FPW)INTEL_ID_28F320C3B:
  290. info->flash_id += FLASH_28F320C3B;
  291. info->sector_count = 71;
  292. info->size = 0x00400000 * (sizeof(FPW)/2);
  293. break; /* => 4 or 8 MB */
  294. case (FPW)INTEL_ID_28F320B3B:
  295. info->flash_id += FLASH_INTEL320B;
  296. info->sector_count = 71;
  297. info->size = 0x00400000 * (sizeof(FPW)/2);
  298. break; /* => 4 or 8 MB */
  299. case (FPW)INTEL_ID_28F640C3B:
  300. info->flash_id += FLASH_28F640C3B;
  301. info->sector_count = 135;
  302. info->size = 0x00800000 * (sizeof(FPW)/2);
  303. break; /* => 8 or 16 MB */
  304. case (FPW)INTEL_ID_28F640B3B:
  305. info->flash_id += FLASH_INTEL640B;
  306. info->sector_count = 135;
  307. info->size = 0x00800000 * (sizeof(FPW)/2);
  308. break; /* => 8 or 16 MB */
  309. default:
  310. info->flash_id = FLASH_UNKNOWN;
  311. info->sector_count = 0;
  312. info->size = 0;
  313. return (0); /* => no or unknown flash */
  314. }
  315. flash_get_offsets((ulong)addr, info);
  316. /* Put FLASH back in read mode */
  317. flash_reset(info);
  318. return (info->size);
  319. }
  320. /*-----------------------------------------------------------------------
  321. */
  322. int flash_erase (flash_info_t *info, int s_first, int s_last)
  323. {
  324. FPWV *addr;
  325. int flag, prot, sect;
  326. int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
  327. ulong start, now, last;
  328. int rcode = 0;
  329. if ((s_first < 0) || (s_first > s_last)) {
  330. if (info->flash_id == FLASH_UNKNOWN) {
  331. printf ("- missing\n");
  332. } else {
  333. printf ("- no sectors to erase\n");
  334. }
  335. return 1;
  336. }
  337. switch (info->flash_id & FLASH_TYPEMASK) {
  338. case FLASH_INTEL800B:
  339. case FLASH_INTEL160B:
  340. case FLASH_INTEL320B:
  341. case FLASH_INTEL640B:
  342. case FLASH_28F800C3B:
  343. case FLASH_28F160C3B:
  344. case FLASH_28F320C3B:
  345. case FLASH_28F640C3B:
  346. case FLASH_AM640U:
  347. break;
  348. case FLASH_UNKNOWN:
  349. default:
  350. printf ("Can't erase unknown flash type %08lx - aborted\n",
  351. info->flash_id);
  352. return 1;
  353. }
  354. prot = 0;
  355. for (sect=s_first; sect<=s_last; ++sect) {
  356. if (info->protect[sect]) {
  357. prot++;
  358. }
  359. }
  360. if (prot) {
  361. printf ("- Warning: %d protected sectors will not be erased!\n",
  362. prot);
  363. } else {
  364. printf ("\n");
  365. }
  366. last = get_timer(0);
  367. /* Start erase on unprotected sectors */
  368. for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
  369. if (info->protect[sect] != 0) /* protected, skip it */
  370. continue;
  371. /* Disable interrupts which might cause a timeout here */
  372. flag = disable_interrupts();
  373. addr = (FPWV *)(info->start[sect]);
  374. if (intel) {
  375. *addr = (FPW)0x00500050; /* clear status register */
  376. *addr = (FPW)0x00200020; /* erase setup */
  377. *addr = (FPW)0x00D000D0; /* erase confirm */
  378. }
  379. else {
  380. /* must be AMD style if not Intel */
  381. FPWV *base; /* first address in bank */
  382. base = (FPWV *)(info->start[0]);
  383. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  384. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  385. base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
  386. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  387. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  388. *addr = (FPW)0x00300030; /* erase sector */
  389. }
  390. /* re-enable interrupts if necessary */
  391. if (flag)
  392. enable_interrupts();
  393. start = get_timer(0);
  394. /* wait at least 50us for AMD, 80us for Intel.
  395. * Let's wait 1 ms.
  396. */
  397. udelay (1000);
  398. while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
  399. if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
  400. printf ("Timeout\n");
  401. if (intel) {
  402. /* suspend erase */
  403. *addr = (FPW)0x00B000B0;
  404. }
  405. flash_reset(info); /* reset to read mode */
  406. rcode = 1; /* failed */
  407. break;
  408. }
  409. /* show that we're waiting */
  410. if ((get_timer(last)) > CFG_HZ) {/* every second */
  411. putc ('.');
  412. last = get_timer(0);
  413. }
  414. }
  415. /* show that we're waiting */
  416. if ((get_timer(last)) > CFG_HZ) { /* every second */
  417. putc ('.');
  418. last = get_timer(0);
  419. }
  420. flash_reset(info); /* reset to read mode */
  421. }
  422. printf (" done\n");
  423. return rcode;
  424. }
  425. /*-----------------------------------------------------------------------
  426. * Copy memory to flash, returns:
  427. * 0 - OK
  428. * 1 - write timeout
  429. * 2 - Flash not erased
  430. */
  431. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  432. {
  433. FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
  434. int bytes; /* number of bytes to program in current word */
  435. int left; /* number of bytes left to program */
  436. int i, res;
  437. for (left = cnt, res = 0;
  438. left > 0 && res == 0;
  439. addr += sizeof(data), left -= sizeof(data) - bytes) {
  440. bytes = addr & (sizeof(data) - 1);
  441. addr &= ~(sizeof(data) - 1);
  442. /* combine source and destination data so can program
  443. * an entire word of 16 or 32 bits
  444. */
  445. for (i = 0; i < sizeof(data); i++) {
  446. data <<= 8;
  447. if (i < bytes || i - bytes >= left )
  448. data += *((uchar *)addr + i);
  449. else
  450. data += *src++;
  451. }
  452. /* write one word to the flash */
  453. switch (info->flash_id & FLASH_VENDMASK) {
  454. case FLASH_MAN_AMD:
  455. res = write_word_amd(info, (FPWV *)addr, data);
  456. break;
  457. case FLASH_MAN_INTEL:
  458. res = write_word_intel(info, (FPWV *)addr, data);
  459. break;
  460. default:
  461. /* unknown flash type, error! */
  462. printf ("missing or unknown FLASH type\n");
  463. res = 1; /* not really a timeout, but gives error */
  464. break;
  465. }
  466. }
  467. return (res);
  468. }
  469. /*-----------------------------------------------------------------------
  470. * Write a word to Flash for AMD FLASH
  471. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  472. * (not an individual chip) is.
  473. *
  474. * returns:
  475. * 0 - OK
  476. * 1 - write timeout
  477. * 2 - Flash not erased
  478. */
  479. static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
  480. {
  481. ulong start;
  482. int flag;
  483. int res = 0; /* result, assume success */
  484. FPWV *base; /* first address in flash bank */
  485. /* Check if Flash is (sufficiently) erased */
  486. if ((*dest & data) != data) {
  487. return (2);
  488. }
  489. base = (FPWV *)(info->start[0]);
  490. /* Disable interrupts which might cause a timeout here */
  491. flag = disable_interrupts();
  492. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  493. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  494. base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
  495. *dest = data; /* start programming the data */
  496. /* re-enable interrupts if necessary */
  497. if (flag)
  498. enable_interrupts();
  499. start = get_timer (0);
  500. /* data polling for D7 */
  501. while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
  502. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  503. *dest = (FPW)0x00F000F0; /* reset bank */
  504. res = 1;
  505. }
  506. }
  507. return (res);
  508. }
  509. /*-----------------------------------------------------------------------
  510. * Write a word to Flash for Intel FLASH
  511. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  512. * (not an individual chip) is.
  513. *
  514. * returns:
  515. * 0 - OK
  516. * 1 - write timeout
  517. * 2 - Flash not erased
  518. */
  519. static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
  520. {
  521. ulong start;
  522. int flag;
  523. int res = 0; /* result, assume success */
  524. /* Check if Flash is (sufficiently) erased */
  525. if ((*dest & data) != data) {
  526. return (2);
  527. }
  528. /* Disable interrupts which might cause a timeout here */
  529. flag = disable_interrupts();
  530. *dest = (FPW)0x00500050; /* clear status register */
  531. *dest = (FPW)0x00FF00FF; /* make sure in read mode */
  532. *dest = (FPW)0x00400040; /* program setup */
  533. *dest = data; /* start programming the data */
  534. /* re-enable interrupts if necessary */
  535. if (flag)
  536. enable_interrupts();
  537. start = get_timer (0);
  538. while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
  539. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  540. *dest = (FPW)0x00B000B0; /* Suspend program */
  541. res = 1;
  542. }
  543. }
  544. if (res == 0 && (*dest & (FPW)0x00100010))
  545. res = 1; /* write failed, time out error is close enough */
  546. *dest = (FPW)0x00500050; /* clear status register */
  547. *dest = (FPW)0x00FF00FF; /* make sure in read mode */
  548. return (res);
  549. }