sequoia.c 15 KB

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  1. /*
  2. * (C) Copyright 2006-2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * (C) Copyright 2006
  6. * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  7. * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <libfdt.h>
  26. #include <fdt_support.h>
  27. #include <ppc4xx.h>
  28. #include <asm/gpio.h>
  29. #include <asm/processor.h>
  30. #include <asm/io.h>
  31. #include <asm/bitops.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  34. ulong flash_get_size (ulong base, int banknum);
  35. int board_early_init_f(void)
  36. {
  37. u32 sdr0_cust0;
  38. u32 sdr0_pfc1, sdr0_pfc2;
  39. u32 reg;
  40. mtdcr(ebccfga, xbcfg);
  41. mtdcr(ebccfgd, 0xb8400000);
  42. /*
  43. * Setup the interrupt controller polarities, triggers, etc.
  44. */
  45. mtdcr(uic0sr, 0xffffffff); /* clear all */
  46. mtdcr(uic0er, 0x00000000); /* disable all */
  47. mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
  48. mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
  49. mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
  50. mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
  51. mtdcr(uic0sr, 0xffffffff); /* clear all */
  52. mtdcr(uic1sr, 0xffffffff); /* clear all */
  53. mtdcr(uic1er, 0x00000000); /* disable all */
  54. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  55. mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
  56. mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
  57. mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
  58. mtdcr(uic1sr, 0xffffffff); /* clear all */
  59. mtdcr(uic2sr, 0xffffffff); /* clear all */
  60. mtdcr(uic2er, 0x00000000); /* disable all */
  61. mtdcr(uic2cr, 0x00000000); /* all non-critical */
  62. mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
  63. mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
  64. mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
  65. mtdcr(uic2sr, 0xffffffff); /* clear all */
  66. /* 50MHz tmrclk */
  67. out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
  68. /* clear write protects */
  69. out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
  70. /* enable Ethernet */
  71. out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
  72. /* enable USB device */
  73. out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
  74. /* select Ethernet (and optionally IIC1) pins */
  75. mfsdr(SDR0_PFC1, sdr0_pfc1);
  76. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
  77. SDR0_PFC1_SELECT_CONFIG_4;
  78. #ifdef CONFIG_I2C_MULTI_BUS
  79. sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
  80. #endif
  81. /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
  82. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  83. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
  84. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
  85. mfsdr(SDR0_PFC2, sdr0_pfc2);
  86. sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
  87. SDR0_PFC2_SELECT_CONFIG_4;
  88. mtsdr(SDR0_PFC2, sdr0_pfc2);
  89. mtsdr(SDR0_PFC1, sdr0_pfc1);
  90. /* PCI arbiter enabled */
  91. mfsdr(sdr_pci0, reg);
  92. mtsdr(sdr_pci0, 0x80000000 | reg);
  93. /* setup NAND FLASH */
  94. mfsdr(SDR0_CUST0, sdr0_cust0);
  95. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  96. SDR0_CUST0_NDFC_ENABLE |
  97. SDR0_CUST0_NDFC_BW_8_BIT |
  98. SDR0_CUST0_NDFC_ARE_MASK |
  99. (0x80000000 >> (28 + CFG_NAND_CS));
  100. mtsdr(SDR0_CUST0, sdr0_cust0);
  101. return 0;
  102. }
  103. int misc_init_r(void)
  104. {
  105. uint pbcr;
  106. int size_val = 0;
  107. u32 reg;
  108. #ifdef CONFIG_440EPX
  109. unsigned long usb2d0cr = 0;
  110. unsigned long usb2phy0cr, usb2h0cr = 0;
  111. unsigned long sdr0_pfc1;
  112. char *act = getenv("usbact");
  113. #endif
  114. /* Re-do flash sizing to get full correct info */
  115. /* adjust flash start and offset */
  116. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  117. gd->bd->bi_flashoffset = 0;
  118. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  119. mtdcr(ebccfga, pb3cr);
  120. #else
  121. mtdcr(ebccfga, pb0cr);
  122. #endif
  123. pbcr = mfdcr(ebccfgd);
  124. size_val = ffs(gd->bd->bi_flashsize) - 21;
  125. pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
  126. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  127. mtdcr(ebccfga, pb3cr);
  128. #else
  129. mtdcr(ebccfga, pb0cr);
  130. #endif
  131. mtdcr(ebccfgd, pbcr);
  132. /*
  133. * Re-check to get correct base address
  134. */
  135. flash_get_size(gd->bd->bi_flashstart, 0);
  136. #ifdef CONFIG_ENV_IS_IN_FLASH
  137. /* Monitor protection ON by default */
  138. (void)flash_protect(FLAG_PROTECT_SET,
  139. -CFG_MONITOR_LEN,
  140. 0xffffffff,
  141. &flash_info[0]);
  142. /* Env protection ON by default */
  143. (void)flash_protect(FLAG_PROTECT_SET,
  144. CFG_ENV_ADDR_REDUND,
  145. CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
  146. &flash_info[0]);
  147. #endif
  148. /*
  149. * USB suff...
  150. */
  151. #ifdef CONFIG_440EPX
  152. if (act == NULL || strcmp(act, "hostdev") == 0) {
  153. /* SDR Setting */
  154. mfsdr(SDR0_PFC1, sdr0_pfc1);
  155. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  156. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  157. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  158. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  159. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  160. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  161. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
  162. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  163. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
  164. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  165. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
  166. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  167. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
  168. /*
  169. * An 8-bit/60MHz interface is the only possible alternative
  170. * when connecting the Device to the PHY
  171. */
  172. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  173. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
  174. /*
  175. * To enable the USB 2.0 Device function
  176. * through the UTMI interface
  177. */
  178. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  179. usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
  180. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  181. sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
  182. mtsdr(SDR0_PFC1, sdr0_pfc1);
  183. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  184. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  185. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  186. /*clear resets*/
  187. udelay (1000);
  188. mtsdr(SDR0_SRST1, 0x00000000);
  189. udelay (1000);
  190. mtsdr(SDR0_SRST0, 0x00000000);
  191. printf("USB: Host(int phy) Device(ext phy)\n");
  192. } else if (strcmp(act, "dev") == 0) {
  193. /*-------------------PATCH-------------------------------*/
  194. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  195. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  196. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  197. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  198. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
  199. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  200. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
  201. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  202. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
  203. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  204. udelay (1000);
  205. mtsdr(SDR0_SRST1, 0x672c6000);
  206. udelay (1000);
  207. mtsdr(SDR0_SRST0, 0x00000080);
  208. udelay (1000);
  209. mtsdr(SDR0_SRST1, 0x60206000);
  210. *(unsigned int *)(0xe0000350) = 0x00000001;
  211. udelay (1000);
  212. mtsdr(SDR0_SRST1, 0x60306000);
  213. /*-------------------PATCH-------------------------------*/
  214. /* SDR Setting */
  215. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  216. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  217. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  218. mfsdr(SDR0_PFC1, sdr0_pfc1);
  219. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  220. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
  221. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  222. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
  223. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  224. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
  225. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  226. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
  227. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  228. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
  229. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  230. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
  231. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  232. usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
  233. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  234. sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
  235. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  236. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  237. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  238. mtsdr(SDR0_PFC1, sdr0_pfc1);
  239. /* clear resets */
  240. udelay (1000);
  241. mtsdr(SDR0_SRST1, 0x00000000);
  242. udelay (1000);
  243. mtsdr(SDR0_SRST0, 0x00000000);
  244. printf("USB: Device(int phy)\n");
  245. }
  246. #endif /* CONFIG_440EPX */
  247. mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
  248. reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
  249. mtsdr(SDR0_SRST1, reg);
  250. /*
  251. * Clear PLB4A0_ACR[WRP]
  252. * This fix will make the MAL burst disabling patch for the Linux
  253. * EMAC driver obsolete.
  254. */
  255. reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
  256. mtdcr(plb4_acr, reg);
  257. return 0;
  258. }
  259. int checkboard(void)
  260. {
  261. char *s = getenv("serial#");
  262. u8 rev;
  263. u8 val;
  264. #ifdef CONFIG_440EPX
  265. printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
  266. #else
  267. printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
  268. #endif
  269. rev = in_8((void *)(CFG_BCSR_BASE + 0));
  270. val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
  271. printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
  272. if (s != NULL) {
  273. puts(", serial# ");
  274. puts(s);
  275. }
  276. putc('\n');
  277. return (0);
  278. }
  279. #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
  280. /*
  281. * Assign interrupts to PCI devices.
  282. */
  283. void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
  284. {
  285. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
  286. }
  287. #endif
  288. /*
  289. * pci_pre_init
  290. *
  291. * This routine is called just prior to registering the hose and gives
  292. * the board the opportunity to check things. Returning a value of zero
  293. * indicates that things are bad & PCI initialization should be aborted.
  294. *
  295. * Different boards may wish to customize the pci controller structure
  296. * (add regions, override default access routines, etc) or perform
  297. * certain pre-initialization actions.
  298. */
  299. #if defined(CONFIG_PCI)
  300. int pci_pre_init(struct pci_controller *hose)
  301. {
  302. unsigned long addr;
  303. /*
  304. * Set priority for all PLB3 devices to 0.
  305. * Set PLB3 arbiter to fair mode.
  306. */
  307. mfsdr(sdr_amp1, addr);
  308. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  309. addr = mfdcr(plb3_acr);
  310. mtdcr(plb3_acr, addr | 0x80000000);
  311. /*
  312. * Set priority for all PLB4 devices to 0.
  313. */
  314. mfsdr(sdr_amp0, addr);
  315. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  316. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  317. mtdcr(plb4_acr, addr);
  318. /*
  319. * Set Nebula PLB4 arbiter to fair mode.
  320. */
  321. /* Segment0 */
  322. addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
  323. addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
  324. addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
  325. addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
  326. mtdcr(plb0_acr, addr);
  327. /* Segment1 */
  328. addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
  329. addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
  330. addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
  331. addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
  332. mtdcr(plb1_acr, addr);
  333. #ifdef CONFIG_PCI_PNP
  334. hose->fixup_irq = sequoia_pci_fixup_irq;
  335. #endif
  336. return 1;
  337. }
  338. #endif /* defined(CONFIG_PCI) */
  339. /*
  340. * pci_target_init
  341. *
  342. * The bootstrap configuration provides default settings for the pci
  343. * inbound map (PIM). But the bootstrap config choices are limited and
  344. * may not be sufficient for a given board.
  345. */
  346. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  347. void pci_target_init(struct pci_controller *hose)
  348. {
  349. /*
  350. * Set up Direct MMIO registers
  351. */
  352. /*
  353. * PowerPC440EPX PCI Master configuration.
  354. * Map one 1Gig range of PLB/processor addresses to PCI memory space.
  355. * PLB address 0xA0000000-0xDFFFFFFF
  356. * ==> PCI address 0xA0000000-0xDFFFFFFF
  357. * Use byte reversed out routines to handle endianess.
  358. * Make this region non-prefetchable.
  359. */
  360. out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
  361. /* - disabled b4 setting */
  362. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  363. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
  364. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  365. out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
  366. /* and enable region */
  367. out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
  368. /* - disabled b4 setting */
  369. out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  370. out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
  371. out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
  372. out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
  373. /* and enable region */
  374. out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  375. out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
  376. out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
  377. out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
  378. /*
  379. * Set up Configuration registers
  380. */
  381. /* Program the board's subsystem id/vendor id */
  382. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  383. CFG_PCI_SUBSYS_VENDORID);
  384. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
  385. /* Configure command register as bus master */
  386. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  387. /* 240nS PCI clock */
  388. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  389. /* No error reporting */
  390. pci_write_config_word(0, PCI_ERREN, 0);
  391. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  392. }
  393. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  394. #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
  395. void pci_master_init(struct pci_controller *hose)
  396. {
  397. unsigned short temp_short;
  398. /*
  399. * Write the PowerPC440 EP PCI Configuration regs.
  400. * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  401. * Enable PowerPC440 EP to act as a PCI memory target (PTM).
  402. */
  403. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  404. pci_write_config_word(0, PCI_COMMAND,
  405. temp_short | PCI_COMMAND_MASTER |
  406. PCI_COMMAND_MEMORY);
  407. }
  408. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
  409. /*
  410. * is_pci_host
  411. *
  412. * This routine is called to determine if a pci scan should be
  413. * performed. With various hardware environments (especially cPCI and
  414. * PPMC) it's insufficient to depend on the state of the arbiter enable
  415. * bit in the strap register, or generic host/adapter assumptions.
  416. *
  417. * Rather than hard-code a bad assumption in the general 440 code, the
  418. * 440 pci code requires the board to decide at runtime.
  419. *
  420. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  421. */
  422. #if defined(CONFIG_PCI)
  423. int is_pci_host(struct pci_controller *hose)
  424. {
  425. /* Cactus is always configured as host. */
  426. return (1);
  427. }
  428. #endif /* defined(CONFIG_PCI) */
  429. #if defined(CONFIG_POST)
  430. /*
  431. * Returns 1 if keys pressed to start the power-on long-running tests
  432. * Called from board_init_f().
  433. */
  434. int post_hotkeys_pressed(void)
  435. {
  436. return 0; /* No hotkeys supported */
  437. }
  438. #endif /* CONFIG_POST */