tegra_nand.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
  5. * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  6. * (C) Copyright 2006 DENX Software Engineering
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <memalign.h>
  11. #include <nand.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/funcmux.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <fdtdec.h>
  18. #include <bouncebuf.h>
  19. #include <dm.h>
  20. #include "tegra_nand.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define NAND_CMD_TIMEOUT_MS 10
  23. #define SKIPPED_SPARE_BYTES 4
  24. /* ECC bytes to be generated for tag data */
  25. #define TAG_ECC_BYTES 4
  26. static const struct udevice_id tegra_nand_dt_ids[] = {
  27. {
  28. .compatible = "nvidia,tegra20-nand",
  29. },
  30. { /* sentinel */ }
  31. };
  32. /* 64 byte oob block info for large page (== 2KB) device
  33. *
  34. * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  35. * Skipped bytes(4)
  36. * Main area Ecc(36)
  37. * Tag data(20)
  38. * Tag data Ecc(4)
  39. *
  40. * Yaffs2 will use 16 tag bytes.
  41. */
  42. static struct nand_ecclayout eccoob = {
  43. .eccbytes = 36,
  44. .eccpos = {
  45. 4, 5, 6, 7, 8, 9, 10, 11, 12,
  46. 13, 14, 15, 16, 17, 18, 19, 20, 21,
  47. 22, 23, 24, 25, 26, 27, 28, 29, 30,
  48. 31, 32, 33, 34, 35, 36, 37, 38, 39,
  49. },
  50. .oobavail = 20,
  51. .oobfree = {
  52. {
  53. .offset = 40,
  54. .length = 20,
  55. },
  56. }
  57. };
  58. enum {
  59. ECC_OK,
  60. ECC_TAG_ERROR = 1 << 0,
  61. ECC_DATA_ERROR = 1 << 1
  62. };
  63. /* Timing parameters */
  64. enum {
  65. FDT_NAND_MAX_TRP_TREA,
  66. FDT_NAND_TWB,
  67. FDT_NAND_MAX_TCR_TAR_TRR,
  68. FDT_NAND_TWHR,
  69. FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  70. FDT_NAND_TWH,
  71. FDT_NAND_TWP,
  72. FDT_NAND_TRH,
  73. FDT_NAND_TADL,
  74. FDT_NAND_TIMING_COUNT
  75. };
  76. /* Information about an attached NAND chip */
  77. struct fdt_nand {
  78. struct nand_ctlr *reg;
  79. int enabled; /* 1 to enable, 0 to disable */
  80. struct gpio_desc wp_gpio; /* write-protect GPIO */
  81. s32 width; /* bit width, normally 8 */
  82. u32 timing[FDT_NAND_TIMING_COUNT];
  83. };
  84. struct nand_drv {
  85. struct nand_ctlr *reg;
  86. struct fdt_nand config;
  87. };
  88. struct tegra_nand_info {
  89. struct udevice *dev;
  90. struct nand_drv nand_ctrl;
  91. struct nand_chip nand_chip;
  92. };
  93. /**
  94. * Wait for command completion
  95. *
  96. * @param reg nand_ctlr structure
  97. * @return
  98. * 1 - Command completed
  99. * 0 - Timeout
  100. */
  101. static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  102. {
  103. u32 reg_val;
  104. int running;
  105. int i;
  106. for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
  107. if ((readl(&reg->command) & CMD_GO) ||
  108. !(readl(&reg->status) & STATUS_RBSY0) ||
  109. !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
  110. udelay(1);
  111. continue;
  112. }
  113. reg_val = readl(&reg->dma_mst_ctrl);
  114. /*
  115. * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
  116. * is set, that means DMA engine is running.
  117. *
  118. * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
  119. * is cleared, indicating DMA transfer completion.
  120. */
  121. running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
  122. DMA_MST_CTRL_EN_B_ENABLE);
  123. if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
  124. return 1;
  125. udelay(1);
  126. }
  127. return 0;
  128. }
  129. /**
  130. * Read one byte from the chip
  131. *
  132. * @param mtd MTD device structure
  133. * @return data byte
  134. *
  135. * Read function for 8bit bus-width
  136. */
  137. static uint8_t read_byte(struct mtd_info *mtd)
  138. {
  139. struct nand_chip *chip = mtd_to_nand(mtd);
  140. struct nand_drv *info;
  141. info = (struct nand_drv *)nand_get_controller_data(chip);
  142. writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
  143. &info->reg->command);
  144. if (!nand_waitfor_cmd_completion(info->reg))
  145. printf("Command timeout\n");
  146. return (uint8_t)readl(&info->reg->resp);
  147. }
  148. /**
  149. * Read len bytes from the chip into a buffer
  150. *
  151. * @param mtd MTD device structure
  152. * @param buf buffer to store data to
  153. * @param len number of bytes to read
  154. *
  155. * Read function for 8bit bus-width
  156. */
  157. static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  158. {
  159. int i, s;
  160. unsigned int reg;
  161. struct nand_chip *chip = mtd_to_nand(mtd);
  162. struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
  163. for (i = 0; i < len; i += 4) {
  164. s = (len - i) > 4 ? 4 : len - i;
  165. writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
  166. ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
  167. &info->reg->command);
  168. if (!nand_waitfor_cmd_completion(info->reg))
  169. puts("Command timeout during read_buf\n");
  170. reg = readl(&info->reg->resp);
  171. memcpy(buf + i, &reg, s);
  172. }
  173. }
  174. /**
  175. * Check NAND status to see if it is ready or not
  176. *
  177. * @param mtd MTD device structure
  178. * @return
  179. * 1 - ready
  180. * 0 - not ready
  181. */
  182. static int nand_dev_ready(struct mtd_info *mtd)
  183. {
  184. struct nand_chip *chip = mtd_to_nand(mtd);
  185. int reg_val;
  186. struct nand_drv *info;
  187. info = (struct nand_drv *)nand_get_controller_data(chip);
  188. reg_val = readl(&info->reg->status);
  189. if (reg_val & STATUS_RBSY0)
  190. return 1;
  191. else
  192. return 0;
  193. }
  194. /* Dummy implementation: we don't support multiple chips */
  195. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  196. {
  197. switch (chipnr) {
  198. case -1:
  199. case 0:
  200. break;
  201. default:
  202. BUG();
  203. }
  204. }
  205. /**
  206. * Clear all interrupt status bits
  207. *
  208. * @param reg nand_ctlr structure
  209. */
  210. static void nand_clear_interrupt_status(struct nand_ctlr *reg)
  211. {
  212. u32 reg_val;
  213. /* Clear interrupt status */
  214. reg_val = readl(&reg->isr);
  215. writel(reg_val, &reg->isr);
  216. }
  217. /**
  218. * Send command to NAND device
  219. *
  220. * @param mtd MTD device structure
  221. * @param command the command to be sent
  222. * @param column the column address for this command, -1 if none
  223. * @param page_addr the page address for this command, -1 if none
  224. */
  225. static void nand_command(struct mtd_info *mtd, unsigned int command,
  226. int column, int page_addr)
  227. {
  228. struct nand_chip *chip = mtd_to_nand(mtd);
  229. struct nand_drv *info;
  230. info = (struct nand_drv *)nand_get_controller_data(chip);
  231. /*
  232. * Write out the command to the device.
  233. *
  234. * Only command NAND_CMD_RESET or NAND_CMD_READID will come
  235. * here before mtd->writesize is initialized.
  236. */
  237. /* Emulate NAND_CMD_READOOB */
  238. if (command == NAND_CMD_READOOB) {
  239. assert(mtd->writesize != 0);
  240. column += mtd->writesize;
  241. command = NAND_CMD_READ0;
  242. }
  243. /* Adjust columns for 16 bit bus-width */
  244. if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
  245. column >>= 1;
  246. nand_clear_interrupt_status(info->reg);
  247. /* Stop DMA engine, clear DMA completion status */
  248. writel(DMA_MST_CTRL_EN_A_DISABLE
  249. | DMA_MST_CTRL_EN_B_DISABLE
  250. | DMA_MST_CTRL_IS_DMA_DONE,
  251. &info->reg->dma_mst_ctrl);
  252. /*
  253. * Program and erase have their own busy handlers
  254. * status and sequential in needs no delay
  255. */
  256. switch (command) {
  257. case NAND_CMD_READID:
  258. writel(NAND_CMD_READID, &info->reg->cmd_reg1);
  259. writel(column & 0xFF, &info->reg->addr_reg1);
  260. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  261. &info->reg->command);
  262. break;
  263. case NAND_CMD_PARAM:
  264. writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
  265. writel(column & 0xFF, &info->reg->addr_reg1);
  266. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  267. &info->reg->command);
  268. break;
  269. case NAND_CMD_READ0:
  270. writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
  271. writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
  272. writel((page_addr << 16) | (column & 0xFFFF),
  273. &info->reg->addr_reg1);
  274. writel(page_addr >> 16, &info->reg->addr_reg2);
  275. return;
  276. case NAND_CMD_SEQIN:
  277. writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
  278. writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
  279. writel((page_addr << 16) | (column & 0xFFFF),
  280. &info->reg->addr_reg1);
  281. writel(page_addr >> 16,
  282. &info->reg->addr_reg2);
  283. return;
  284. case NAND_CMD_PAGEPROG:
  285. return;
  286. case NAND_CMD_ERASE1:
  287. writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
  288. writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
  289. writel(page_addr, &info->reg->addr_reg1);
  290. writel(CMD_GO | CMD_CLE | CMD_ALE |
  291. CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
  292. &info->reg->command);
  293. break;
  294. case NAND_CMD_ERASE2:
  295. return;
  296. case NAND_CMD_STATUS:
  297. writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
  298. writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
  299. | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
  300. | CMD_CE0,
  301. &info->reg->command);
  302. break;
  303. case NAND_CMD_RESET:
  304. writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
  305. writel(CMD_GO | CMD_CLE | CMD_CE0,
  306. &info->reg->command);
  307. break;
  308. case NAND_CMD_RNDOUT:
  309. default:
  310. printf("%s: Unsupported command %d\n", __func__, command);
  311. return;
  312. }
  313. if (!nand_waitfor_cmd_completion(info->reg))
  314. printf("Command 0x%02X timeout\n", command);
  315. }
  316. /**
  317. * Check whether the pointed buffer are all 0xff (blank).
  318. *
  319. * @param buf data buffer for blank check
  320. * @param len length of the buffer in byte
  321. * @return
  322. * 1 - blank
  323. * 0 - non-blank
  324. */
  325. static int blank_check(u8 *buf, int len)
  326. {
  327. int i;
  328. for (i = 0; i < len; i++)
  329. if (buf[i] != 0xFF)
  330. return 0;
  331. return 1;
  332. }
  333. /**
  334. * After a DMA transfer for read, we call this function to see whether there
  335. * is any uncorrectable error on the pointed data buffer or oob buffer.
  336. *
  337. * @param reg nand_ctlr structure
  338. * @param databuf data buffer
  339. * @param a_len data buffer length
  340. * @param oobbuf oob buffer
  341. * @param b_len oob buffer length
  342. * @return
  343. * ECC_OK - no ECC error or correctable ECC error
  344. * ECC_TAG_ERROR - uncorrectable tag ECC error
  345. * ECC_DATA_ERROR - uncorrectable data ECC error
  346. * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
  347. */
  348. static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
  349. int a_len, u8 *oobbuf, int b_len)
  350. {
  351. int return_val = ECC_OK;
  352. u32 reg_val;
  353. if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
  354. return ECC_OK;
  355. /*
  356. * Area A is used for the data block (databuf). Area B is used for
  357. * the spare block (oobbuf)
  358. */
  359. reg_val = readl(&reg->dec_status);
  360. if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
  361. reg_val = readl(&reg->bch_dec_status_buf);
  362. /*
  363. * If uncorrectable error occurs on data area, then see whether
  364. * they are all FF. If all are FF, it's a blank page.
  365. * Not error.
  366. */
  367. if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
  368. !blank_check(databuf, a_len))
  369. return_val |= ECC_DATA_ERROR;
  370. }
  371. if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
  372. reg_val = readl(&reg->bch_dec_status_buf);
  373. /*
  374. * If uncorrectable error occurs on tag area, then see whether
  375. * they are all FF. If all are FF, it's a blank page.
  376. * Not error.
  377. */
  378. if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
  379. !blank_check(oobbuf, b_len))
  380. return_val |= ECC_TAG_ERROR;
  381. }
  382. return return_val;
  383. }
  384. /**
  385. * Set GO bit to send command to device
  386. *
  387. * @param reg nand_ctlr structure
  388. */
  389. static void start_command(struct nand_ctlr *reg)
  390. {
  391. u32 reg_val;
  392. reg_val = readl(&reg->command);
  393. reg_val |= CMD_GO;
  394. writel(reg_val, &reg->command);
  395. }
  396. /**
  397. * Clear command GO bit, DMA GO bit, and DMA completion status
  398. *
  399. * @param reg nand_ctlr structure
  400. */
  401. static void stop_command(struct nand_ctlr *reg)
  402. {
  403. /* Stop command */
  404. writel(0, &reg->command);
  405. /* Stop DMA engine and clear DMA completion status */
  406. writel(DMA_MST_CTRL_GO_DISABLE
  407. | DMA_MST_CTRL_IS_DMA_DONE,
  408. &reg->dma_mst_ctrl);
  409. }
  410. /**
  411. * Set up NAND bus width and page size
  412. *
  413. * @param info nand_info structure
  414. * @param *reg_val address of reg_val
  415. * @return 0 if ok, -1 on error
  416. */
  417. static int set_bus_width_page_size(struct mtd_info *our_mtd,
  418. struct fdt_nand *config, u32 *reg_val)
  419. {
  420. if (config->width == 8)
  421. *reg_val = CFG_BUS_WIDTH_8BIT;
  422. else if (config->width == 16)
  423. *reg_val = CFG_BUS_WIDTH_16BIT;
  424. else {
  425. debug("%s: Unsupported bus width %d\n", __func__,
  426. config->width);
  427. return -1;
  428. }
  429. if (our_mtd->writesize == 512)
  430. *reg_val |= CFG_PAGE_SIZE_512;
  431. else if (our_mtd->writesize == 2048)
  432. *reg_val |= CFG_PAGE_SIZE_2048;
  433. else if (our_mtd->writesize == 4096)
  434. *reg_val |= CFG_PAGE_SIZE_4096;
  435. else {
  436. debug("%s: Unsupported page size %d\n", __func__,
  437. our_mtd->writesize);
  438. return -1;
  439. }
  440. return 0;
  441. }
  442. /**
  443. * Page read/write function
  444. *
  445. * @param mtd mtd info structure
  446. * @param chip nand chip info structure
  447. * @param buf data buffer
  448. * @param page page number
  449. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  450. * @param is_writing 0 for read, 1 for write
  451. * @return 0 when successfully completed
  452. * -EIO when command timeout
  453. */
  454. static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
  455. uint8_t *buf, int page, int with_ecc, int is_writing)
  456. {
  457. u32 reg_val;
  458. int tag_size;
  459. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  460. /* 4*128=512 (byte) is the value that our HW can support. */
  461. ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
  462. char *tag_ptr;
  463. struct nand_drv *info;
  464. struct fdt_nand *config;
  465. unsigned int bbflags;
  466. struct bounce_buffer bbstate, bbstate_oob;
  467. if ((uintptr_t)buf & 0x03) {
  468. printf("buf %p has to be 4-byte aligned\n", buf);
  469. return -EINVAL;
  470. }
  471. info = (struct nand_drv *)nand_get_controller_data(chip);
  472. config = &info->config;
  473. if (set_bus_width_page_size(mtd, config, &reg_val))
  474. return -EINVAL;
  475. /* Need to be 4-byte aligned */
  476. tag_ptr = (char *)tag_buf;
  477. stop_command(info->reg);
  478. if (is_writing)
  479. bbflags = GEN_BB_READ;
  480. else
  481. bbflags = GEN_BB_WRITE;
  482. bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
  483. bbflags);
  484. writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
  485. writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
  486. /* Set ECC selection, configure ECC settings */
  487. if (with_ecc) {
  488. if (is_writing)
  489. memcpy(tag_ptr, chip->oob_poi + free->offset,
  490. chip->ecc.layout->oobavail + TAG_ECC_BYTES);
  491. tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
  492. reg_val |= (CFG_SKIP_SPARE_SEL_4
  493. | CFG_SKIP_SPARE_ENABLE
  494. | CFG_HW_ECC_CORRECTION_ENABLE
  495. | CFG_ECC_EN_TAG_DISABLE
  496. | CFG_HW_ECC_SEL_RS
  497. | CFG_HW_ECC_ENABLE
  498. | CFG_TVAL4
  499. | (tag_size - 1));
  500. if (!is_writing)
  501. tag_size += SKIPPED_SPARE_BYTES;
  502. bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
  503. bbflags);
  504. } else {
  505. tag_size = mtd->oobsize;
  506. reg_val |= (CFG_SKIP_SPARE_DISABLE
  507. | CFG_HW_ECC_CORRECTION_DISABLE
  508. | CFG_ECC_EN_TAG_DISABLE
  509. | CFG_HW_ECC_DISABLE
  510. | (tag_size - 1));
  511. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
  512. tag_size, bbflags);
  513. }
  514. writel(reg_val, &info->reg->config);
  515. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  516. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  517. writel(tag_size - 1, &info->reg->dma_cfg_b);
  518. nand_clear_interrupt_status(info->reg);
  519. reg_val = CMD_CLE | CMD_ALE
  520. | CMD_SEC_CMD
  521. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  522. | CMD_A_VALID
  523. | CMD_B_VALID
  524. | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
  525. | CMD_CE0;
  526. if (!is_writing)
  527. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  528. else
  529. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  530. writel(reg_val, &info->reg->command);
  531. /* Setup DMA engine */
  532. reg_val = DMA_MST_CTRL_GO_ENABLE
  533. | DMA_MST_CTRL_BURST_8WORDS
  534. | DMA_MST_CTRL_EN_A_ENABLE
  535. | DMA_MST_CTRL_EN_B_ENABLE;
  536. if (!is_writing)
  537. reg_val |= DMA_MST_CTRL_DIR_READ;
  538. else
  539. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  540. writel(reg_val, &info->reg->dma_mst_ctrl);
  541. start_command(info->reg);
  542. if (!nand_waitfor_cmd_completion(info->reg)) {
  543. if (!is_writing)
  544. printf("Read Page 0x%X timeout ", page);
  545. else
  546. printf("Write Page 0x%X timeout ", page);
  547. if (with_ecc)
  548. printf("with ECC");
  549. else
  550. printf("without ECC");
  551. printf("\n");
  552. return -EIO;
  553. }
  554. bounce_buffer_stop(&bbstate_oob);
  555. bounce_buffer_stop(&bbstate);
  556. if (with_ecc && !is_writing) {
  557. memcpy(chip->oob_poi, tag_ptr,
  558. SKIPPED_SPARE_BYTES);
  559. memcpy(chip->oob_poi + free->offset,
  560. tag_ptr + SKIPPED_SPARE_BYTES,
  561. chip->ecc.layout->oobavail);
  562. reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
  563. 1 << chip->page_shift,
  564. (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
  565. chip->ecc.layout->oobavail);
  566. if (reg_val & ECC_TAG_ERROR)
  567. printf("Read Page 0x%X tag ECC error\n", page);
  568. if (reg_val & ECC_DATA_ERROR)
  569. printf("Read Page 0x%X data ECC error\n",
  570. page);
  571. if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
  572. return -EIO;
  573. }
  574. return 0;
  575. }
  576. /**
  577. * Hardware ecc based page read function
  578. *
  579. * @param mtd mtd info structure
  580. * @param chip nand chip info structure
  581. * @param buf buffer to store read data
  582. * @param page page number to read
  583. * @return 0 when successfully completed
  584. * -EIO when command timeout
  585. */
  586. static int nand_read_page_hwecc(struct mtd_info *mtd,
  587. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  588. {
  589. return nand_rw_page(mtd, chip, buf, page, 1, 0);
  590. }
  591. /**
  592. * Hardware ecc based page write function
  593. *
  594. * @param mtd mtd info structure
  595. * @param chip nand chip info structure
  596. * @param buf data buffer
  597. */
  598. static int nand_write_page_hwecc(struct mtd_info *mtd,
  599. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  600. int page)
  601. {
  602. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
  603. return 0;
  604. }
  605. /**
  606. * Read raw page data without ecc
  607. *
  608. * @param mtd mtd info structure
  609. * @param chip nand chip info structure
  610. * @param buf buffer to store read data
  611. * @param page page number to read
  612. * @return 0 when successfully completed
  613. * -EINVAL when chip->oob_poi is not double-word aligned
  614. * -EIO when command timeout
  615. */
  616. static int nand_read_page_raw(struct mtd_info *mtd,
  617. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  618. {
  619. return nand_rw_page(mtd, chip, buf, page, 0, 0);
  620. }
  621. /**
  622. * Raw page write function
  623. *
  624. * @param mtd mtd info structure
  625. * @param chip nand chip info structure
  626. * @param buf data buffer
  627. */
  628. static int nand_write_page_raw(struct mtd_info *mtd,
  629. struct nand_chip *chip, const uint8_t *buf,
  630. int oob_required, int page)
  631. {
  632. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
  633. return 0;
  634. }
  635. /**
  636. * OOB data read/write function
  637. *
  638. * @param mtd mtd info structure
  639. * @param chip nand chip info structure
  640. * @param page page number to read
  641. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  642. * @param is_writing 0 for read, 1 for write
  643. * @return 0 when successfully completed
  644. * -EINVAL when chip->oob_poi is not double-word aligned
  645. * -EIO when command timeout
  646. */
  647. static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
  648. int page, int with_ecc, int is_writing)
  649. {
  650. u32 reg_val;
  651. int tag_size;
  652. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  653. struct nand_drv *info;
  654. unsigned int bbflags;
  655. struct bounce_buffer bbstate_oob;
  656. if (((int)chip->oob_poi) & 0x03)
  657. return -EINVAL;
  658. info = (struct nand_drv *)nand_get_controller_data(chip);
  659. if (set_bus_width_page_size(mtd, &info->config, &reg_val))
  660. return -EINVAL;
  661. stop_command(info->reg);
  662. /* Set ECC selection */
  663. tag_size = mtd->oobsize;
  664. if (with_ecc)
  665. reg_val |= CFG_ECC_EN_TAG_ENABLE;
  666. else
  667. reg_val |= (CFG_ECC_EN_TAG_DISABLE);
  668. reg_val |= ((tag_size - 1) |
  669. CFG_SKIP_SPARE_DISABLE |
  670. CFG_HW_ECC_CORRECTION_DISABLE |
  671. CFG_HW_ECC_DISABLE);
  672. writel(reg_val, &info->reg->config);
  673. if (is_writing && with_ecc)
  674. tag_size -= TAG_ECC_BYTES;
  675. if (is_writing)
  676. bbflags = GEN_BB_READ;
  677. else
  678. bbflags = GEN_BB_WRITE;
  679. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
  680. bbflags);
  681. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  682. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  683. writel(tag_size - 1, &info->reg->dma_cfg_b);
  684. nand_clear_interrupt_status(info->reg);
  685. reg_val = CMD_CLE | CMD_ALE
  686. | CMD_SEC_CMD
  687. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  688. | CMD_B_VALID
  689. | CMD_CE0;
  690. if (!is_writing)
  691. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  692. else
  693. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  694. writel(reg_val, &info->reg->command);
  695. /* Setup DMA engine */
  696. reg_val = DMA_MST_CTRL_GO_ENABLE
  697. | DMA_MST_CTRL_BURST_8WORDS
  698. | DMA_MST_CTRL_EN_B_ENABLE;
  699. if (!is_writing)
  700. reg_val |= DMA_MST_CTRL_DIR_READ;
  701. else
  702. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  703. writel(reg_val, &info->reg->dma_mst_ctrl);
  704. start_command(info->reg);
  705. if (!nand_waitfor_cmd_completion(info->reg)) {
  706. if (!is_writing)
  707. printf("Read OOB of Page 0x%X timeout\n", page);
  708. else
  709. printf("Write OOB of Page 0x%X timeout\n", page);
  710. return -EIO;
  711. }
  712. bounce_buffer_stop(&bbstate_oob);
  713. if (with_ecc && !is_writing) {
  714. reg_val = (u32)check_ecc_error(info->reg, 0, 0,
  715. (u8 *)(chip->oob_poi + free->offset),
  716. chip->ecc.layout->oobavail);
  717. if (reg_val & ECC_TAG_ERROR)
  718. printf("Read OOB of Page 0x%X tag ECC error\n", page);
  719. }
  720. return 0;
  721. }
  722. /**
  723. * OOB data read function
  724. *
  725. * @param mtd mtd info structure
  726. * @param chip nand chip info structure
  727. * @param page page number to read
  728. */
  729. static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  730. int page)
  731. {
  732. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  733. nand_rw_oob(mtd, chip, page, 0, 0);
  734. return 0;
  735. }
  736. /**
  737. * OOB data write function
  738. *
  739. * @param mtd mtd info structure
  740. * @param chip nand chip info structure
  741. * @param page page number to write
  742. * @return 0 when successfully completed
  743. * -EINVAL when chip->oob_poi is not double-word aligned
  744. * -EIO when command timeout
  745. */
  746. static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  747. int page)
  748. {
  749. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  750. return nand_rw_oob(mtd, chip, page, 0, 1);
  751. }
  752. /**
  753. * Set up NAND memory timings according to the provided parameters
  754. *
  755. * @param timing Timing parameters
  756. * @param reg NAND controller register address
  757. */
  758. static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
  759. struct nand_ctlr *reg)
  760. {
  761. u32 reg_val, clk_rate, clk_period, time_val;
  762. clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
  763. CLOCK_ID_PERIPH) / 1000000;
  764. clk_period = 1000 / clk_rate;
  765. reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  766. TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
  767. reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
  768. TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
  769. time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
  770. if (time_val > 2)
  771. reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
  772. TIMING_TCR_TAR_TRR_CNT_MASK;
  773. reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
  774. TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
  775. time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
  776. if (time_val > 1)
  777. reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
  778. TIMING_TCS_CNT_MASK;
  779. reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
  780. TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
  781. reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
  782. TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
  783. reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
  784. TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
  785. reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  786. TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
  787. writel(reg_val, &reg->timing);
  788. reg_val = 0;
  789. time_val = timing[FDT_NAND_TADL] / clk_period;
  790. if (time_val > 2)
  791. reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
  792. writel(reg_val, &reg->timing2);
  793. }
  794. /**
  795. * Decode NAND parameters from the device tree
  796. *
  797. * @param dev Driver model device
  798. * @param config Device tree NAND configuration
  799. * @return 0 if ok, -ve on error (FDT_ERR_...)
  800. */
  801. static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
  802. {
  803. int err;
  804. config->reg = (struct nand_ctlr *)dev_read_addr(dev);
  805. config->enabled = dev_read_enabled(dev);
  806. config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
  807. err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
  808. GPIOD_IS_OUT);
  809. if (err)
  810. return err;
  811. err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
  812. FDT_NAND_TIMING_COUNT);
  813. if (err < 0)
  814. return err;
  815. return 0;
  816. }
  817. static int tegra_probe(struct udevice *dev)
  818. {
  819. struct tegra_nand_info *tegra = dev_get_priv(dev);
  820. struct nand_chip *nand = &tegra->nand_chip;
  821. struct nand_drv *info = &tegra->nand_ctrl;
  822. struct fdt_nand *config = &info->config;
  823. struct mtd_info *our_mtd;
  824. int ret;
  825. if (fdt_decode_nand(dev, config)) {
  826. printf("Could not decode nand-flash in device tree\n");
  827. return -1;
  828. }
  829. if (!config->enabled)
  830. return -1;
  831. info->reg = config->reg;
  832. nand->ecc.mode = NAND_ECC_HW;
  833. nand->ecc.layout = &eccoob;
  834. nand->options = LP_OPTIONS;
  835. nand->cmdfunc = nand_command;
  836. nand->read_byte = read_byte;
  837. nand->read_buf = read_buf;
  838. nand->ecc.read_page = nand_read_page_hwecc;
  839. nand->ecc.write_page = nand_write_page_hwecc;
  840. nand->ecc.read_page_raw = nand_read_page_raw;
  841. nand->ecc.write_page_raw = nand_write_page_raw;
  842. nand->ecc.read_oob = nand_read_oob;
  843. nand->ecc.write_oob = nand_write_oob;
  844. nand->ecc.strength = 1;
  845. nand->select_chip = nand_select_chip;
  846. nand->dev_ready = nand_dev_ready;
  847. nand_set_controller_data(nand, &tegra->nand_ctrl);
  848. /* Disable subpage writes as we do not provide ecc->hwctl */
  849. nand->options |= NAND_NO_SUBPAGE_WRITE;
  850. /* Adjust controller clock rate */
  851. clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
  852. /* Adjust timing for NAND device */
  853. setup_timing(config->timing, info->reg);
  854. dm_gpio_set_value(&config->wp_gpio, 1);
  855. our_mtd = nand_to_mtd(nand);
  856. ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  857. if (ret)
  858. return ret;
  859. nand->ecc.size = our_mtd->writesize;
  860. nand->ecc.bytes = our_mtd->oobsize;
  861. ret = nand_scan_tail(our_mtd);
  862. if (ret)
  863. return ret;
  864. ret = nand_register(0, our_mtd);
  865. if (ret) {
  866. dev_err(dev, "Failed to register MTD: %d\n", ret);
  867. return ret;
  868. }
  869. return 0;
  870. }
  871. U_BOOT_DRIVER(tegra_nand) = {
  872. .name = "tegra-nand",
  873. .id = UCLASS_MTD,
  874. .of_match = tegra_nand_dt_ids,
  875. .probe = tegra_probe,
  876. .priv_auto_alloc_size = sizeof(struct tegra_nand_info),
  877. };
  878. void board_nand_init(void)
  879. {
  880. struct udevice *dev;
  881. int ret;
  882. ret = uclass_get_device_by_driver(UCLASS_MTD,
  883. DM_GET_DRIVER(tegra_nand), &dev);
  884. if (ret && ret != -ENODEV)
  885. pr_err("Failed to initialize %s. (error %d)\n", dev->name,
  886. ret);
  887. }