fsl_ifc_spl.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NAND boot for Freescale Integrated Flash Controller, NAND FCM
  4. *
  5. * Copyright 2011 Freescale Semiconductor, Inc.
  6. * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <fsl_ifc.h>
  11. #include <linux/mtd/rawnand.h>
  12. #ifdef CONFIG_CHAIN_OF_TRUST
  13. #include <fsl_validate.h>
  14. #endif
  15. static inline int is_blank(uchar *addr, int page_size)
  16. {
  17. int i;
  18. for (i = 0; i < page_size; i++) {
  19. if (__raw_readb(&addr[i]) != 0xff)
  20. return 0;
  21. }
  22. /*
  23. * For the SPL, don't worry about uncorrectable errors
  24. * where the main area is all FFs but shouldn't be.
  25. */
  26. return 1;
  27. }
  28. /* returns nonzero if entire page is blank */
  29. static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  30. unsigned int bufnum, int page_size)
  31. {
  32. u32 reg = eccstat[bufnum / 4];
  33. int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  34. if (errors == 0xf) { /* uncorrectable */
  35. /* Blank pages fail hw ECC checks */
  36. if (is_blank(buf, page_size))
  37. return 1;
  38. puts("ecc error\n");
  39. for (;;)
  40. ;
  41. }
  42. return 0;
  43. }
  44. static inline struct fsl_ifc_runtime *runtime_regs_address(void)
  45. {
  46. struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
  47. int ver = 0;
  48. ver = ifc_in32(&regs.gregs->ifc_rev);
  49. if (ver >= FSL_IFC_V2_0_0)
  50. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  51. else
  52. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  53. return regs.rregs;
  54. }
  55. static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  56. {
  57. struct fsl_ifc_runtime *ifc = runtime_regs_address();
  58. u32 status;
  59. u32 eccstat[8];
  60. int bufperpage = page_size / 512;
  61. int bufnum_end, i;
  62. bufnum *= bufperpage;
  63. bufnum_end = bufnum + bufperpage - 1;
  64. do {
  65. status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  66. } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  67. if (status & IFC_NAND_EVTER_STAT_FTOER) {
  68. puts("flash time out error\n");
  69. for (;;)
  70. ;
  71. }
  72. for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  73. eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  74. for (i = bufnum; i <= bufnum_end; i++) {
  75. if (check_read_ecc(buf, eccstat, i, page_size))
  76. break;
  77. }
  78. ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
  79. }
  80. static inline int bad_block(uchar *marker, int port_size)
  81. {
  82. if (port_size == 8)
  83. return __raw_readb(marker) != 0xff;
  84. else
  85. return __raw_readw((u16 *)marker) != 0xffff;
  86. }
  87. int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  88. {
  89. struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
  90. struct fsl_ifc_runtime *ifc = NULL;
  91. uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  92. int page_size;
  93. int port_size;
  94. int pages_per_blk;
  95. int blk_size;
  96. int bad_marker = 0;
  97. int bufnum_mask, bufnum, ver = 0;
  98. int csor, cspr;
  99. int pos = 0;
  100. int j = 0;
  101. int sram_addr;
  102. int pg_no;
  103. uchar *dst = vdst;
  104. ifc = runtime_regs_address();
  105. /* Get NAND Flash configuration */
  106. csor = CONFIG_SYS_NAND_CSOR;
  107. cspr = CONFIG_SYS_NAND_CSPR;
  108. port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
  109. if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
  110. page_size = 8192;
  111. bufnum_mask = 0x0;
  112. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
  113. page_size = 4096;
  114. bufnum_mask = 0x1;
  115. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
  116. page_size = 2048;
  117. bufnum_mask = 0x3;
  118. } else {
  119. page_size = 512;
  120. bufnum_mask = 0xf;
  121. if (port_size == 8)
  122. bad_marker = 5;
  123. }
  124. ver = ifc_in32(&gregs->ifc_rev);
  125. if (ver >= FSL_IFC_V2_0_0)
  126. bufnum_mask = (bufnum_mask * 2) + 1;
  127. pages_per_blk =
  128. 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
  129. blk_size = pages_per_blk * page_size;
  130. /* Open Full SRAM mapping for spare are access */
  131. ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
  132. /* Clear Boot events */
  133. ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
  134. /* Program FIR/FCR for Large/Small page */
  135. if (page_size > 512) {
  136. ifc_out32(&ifc->ifc_nand.nand_fir0,
  137. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  138. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  139. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  140. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  141. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
  142. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  143. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  144. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  145. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  146. } else {
  147. ifc_out32(&ifc->ifc_nand.nand_fir0,
  148. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  149. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  150. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  151. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
  152. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  153. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  154. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  155. }
  156. /* Program FBCR = 0 for full page read */
  157. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  158. /* Read and copy u-boot on SDRAM from NAND device, In parallel
  159. * check for Bad block if found skip it and read continue to
  160. * next Block
  161. */
  162. while (pos < uboot_size) {
  163. int i = 0;
  164. do {
  165. pg_no = offs / page_size;
  166. bufnum = pg_no & bufnum_mask;
  167. sram_addr = bufnum * page_size * 2;
  168. ifc_out32(&ifc->ifc_nand.row0, pg_no);
  169. ifc_out32(&ifc->ifc_nand.col0, 0);
  170. /* start read */
  171. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  172. IFC_NAND_SEQ_STRT_FIR_STRT);
  173. /* wait for read to complete */
  174. nand_wait(&buf[sram_addr], bufnum, page_size);
  175. /*
  176. * If either of the first two pages are marked bad,
  177. * continue to the next block.
  178. */
  179. if (i++ < 2 &&
  180. bad_block(&buf[sram_addr + page_size + bad_marker],
  181. port_size)) {
  182. puts("skipping\n");
  183. offs = (offs + blk_size) & ~(blk_size - 1);
  184. pos &= ~(blk_size - 1);
  185. break;
  186. }
  187. for (j = 0; j < page_size; j++)
  188. dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
  189. pos += page_size;
  190. offs += page_size;
  191. } while ((offs & (blk_size - 1)) && (pos < uboot_size));
  192. }
  193. return 0;
  194. }
  195. /*
  196. * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
  197. * configured and available since this code loads the main U-Boot image
  198. * from NAND into SDRAM and starts from there.
  199. */
  200. void nand_boot(void)
  201. {
  202. __attribute__((noreturn)) void (*uboot)(void);
  203. /*
  204. * Load U-Boot image from NAND into RAM
  205. */
  206. nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
  207. CONFIG_SYS_NAND_U_BOOT_SIZE,
  208. (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
  209. #ifdef CONFIG_NAND_ENV_DST
  210. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  211. (uchar *)CONFIG_NAND_ENV_DST);
  212. #ifdef CONFIG_ENV_OFFSET_REDUND
  213. nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
  214. (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
  215. #endif
  216. #endif
  217. /*
  218. * Jump to U-Boot image
  219. */
  220. #ifdef CONFIG_SPL_FLUSH_IMAGE
  221. /*
  222. * Clean d-cache and invalidate i-cache, to
  223. * make sure that no stale data is executed.
  224. */
  225. flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
  226. #endif
  227. #ifdef CONFIG_CHAIN_OF_TRUST
  228. /*
  229. * U-Boot header is appended at end of U-boot image, so
  230. * calculate U-boot header address using U-boot header size.
  231. */
  232. #define CONFIG_U_BOOT_HDR_ADDR \
  233. ((CONFIG_SYS_NAND_U_BOOT_START + \
  234. CONFIG_SYS_NAND_U_BOOT_SIZE) - \
  235. CONFIG_U_BOOT_HDR_SIZE)
  236. spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
  237. CONFIG_SYS_NAND_U_BOOT_START);
  238. /*
  239. * In case of failure in validation, spl_validate_uboot would
  240. * not return back in case of Production environment with ITS=1.
  241. * Thus U-Boot will not start.
  242. * In Development environment (ITS=0 and SB_EN=1), the function
  243. * may return back in case of non-fatal failures.
  244. */
  245. #endif
  246. uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
  247. uboot();
  248. }
  249. #ifndef CONFIG_SPL_NAND_INIT
  250. void nand_init(void)
  251. {
  252. }
  253. void nand_deselect(void)
  254. {
  255. }
  256. #endif