Kconfig 8.6 KB

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  1. menuconfig NAND
  2. bool "Raw NAND Device Support"
  3. if NAND
  4. config SYS_NAND_SELF_INIT
  5. bool
  6. help
  7. This option, if enabled, provides more flexible and linux-like
  8. NAND initialization process.
  9. config NAND_ATMEL
  10. bool "Support Atmel NAND controller"
  11. imply SYS_NAND_USE_FLASH_BBT
  12. help
  13. Enable this driver for NAND flash platforms using an Atmel NAND
  14. controller.
  15. config NAND_DAVINCI
  16. bool "Support TI Davinci NAND controller"
  17. help
  18. Enable this driver for NAND flash controllers available in TI Davinci
  19. and Keystone2 platforms
  20. config NAND_DENALI
  21. bool
  22. select SYS_NAND_SELF_INIT
  23. imply CMD_NAND
  24. config NAND_DENALI_DT
  25. bool "Support Denali NAND controller as a DT device"
  26. select NAND_DENALI
  27. depends on OF_CONTROL && DM
  28. help
  29. Enable the driver for NAND flash on platforms using a Denali NAND
  30. controller as a DT device.
  31. config NAND_DENALI_SPARE_AREA_SKIP_BYTES
  32. int "Number of bytes skipped in OOB area"
  33. depends on NAND_DENALI
  34. range 0 63
  35. help
  36. This option specifies the number of bytes to skip from the beginning
  37. of OOB area before last ECC sector data starts. This is potentially
  38. used to preserve the bad block marker in the OOB area.
  39. config NAND_LPC32XX_SLC
  40. bool "Support LPC32XX_SLC controller"
  41. help
  42. Enable the LPC32XX SLC NAND controller.
  43. config NAND_OMAP_GPMC
  44. bool "Support OMAP GPMC NAND controller"
  45. depends on ARCH_OMAP2PLUS
  46. help
  47. Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
  48. GPMC controller is used for parallel NAND flash devices, and can
  49. do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
  50. and BCH16 ECC algorithms.
  51. config NAND_OMAP_GPMC_PREFETCH
  52. bool "Enable GPMC Prefetch"
  53. depends on NAND_OMAP_GPMC
  54. default y
  55. help
  56. On OMAP platforms that use the GPMC controller
  57. (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
  58. uses the prefetch mode to speed up read operations.
  59. config NAND_OMAP_ELM
  60. bool "Enable ELM driver for OMAPxx and AMxx platforms."
  61. depends on NAND_OMAP_GPMC && !OMAP34XX
  62. help
  63. ELM controller is used for ECC error detection (not ECC calculation)
  64. of BCH4, BCH8 and BCH16 ECC algorithms.
  65. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  66. thus such SoC platforms need to depend on software library for ECC error
  67. detection. However ECC calculation on such plaforms would still be
  68. done by GPMC controller.
  69. config NAND_VF610_NFC
  70. bool "Support for Freescale NFC for VF610"
  71. select SYS_NAND_SELF_INIT
  72. imply CMD_NAND
  73. help
  74. Enables support for NAND Flash Controller on some Freescale
  75. processors like the VF610, MCF54418 or Kinetis K70.
  76. The driver supports a maximum 2k page size. The driver
  77. currently does not support hardware ECC.
  78. choice
  79. prompt "Hardware ECC strength"
  80. depends on NAND_VF610_NFC
  81. default SYS_NAND_VF610_NFC_45_ECC_BYTES
  82. help
  83. Select the ECC strength used in the hardware BCH ECC block.
  84. config SYS_NAND_VF610_NFC_45_ECC_BYTES
  85. bool "24-error correction (45 ECC bytes)"
  86. config SYS_NAND_VF610_NFC_60_ECC_BYTES
  87. bool "32-error correction (60 ECC bytes)"
  88. endchoice
  89. config NAND_PXA3XX
  90. bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
  91. select SYS_NAND_SELF_INIT
  92. imply CMD_NAND
  93. help
  94. This enables the driver for the NAND flash device found on
  95. PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
  96. config NAND_SUNXI
  97. bool "Support for NAND on Allwinner SoCs"
  98. default ARCH_SUNXI
  99. depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
  100. select SYS_NAND_SELF_INIT
  101. select SYS_NAND_U_BOOT_LOCATIONS
  102. select SPL_NAND_SUPPORT
  103. imply CMD_NAND
  104. ---help---
  105. Enable support for NAND. This option enables the standard and
  106. SPL drivers.
  107. The SPL driver only supports reading from the NAND using DMA
  108. transfers.
  109. if NAND_SUNXI
  110. config NAND_SUNXI_SPL_ECC_STRENGTH
  111. int "Allwinner NAND SPL ECC Strength"
  112. default 64
  113. config NAND_SUNXI_SPL_ECC_SIZE
  114. int "Allwinner NAND SPL ECC Step Size"
  115. default 1024
  116. config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
  117. int "Allwinner NAND SPL Usable Page Size"
  118. default 1024
  119. endif
  120. config NAND_ARASAN
  121. bool "Configure Arasan Nand"
  122. select SYS_NAND_SELF_INIT
  123. imply CMD_NAND
  124. help
  125. This enables Nand driver support for Arasan nand flash
  126. controller. This uses the hardware ECC for read and
  127. write operations.
  128. config NAND_MXC
  129. bool "MXC NAND support"
  130. depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
  131. imply CMD_NAND
  132. help
  133. This enables the NAND driver for the NAND flash controller on the
  134. i.MX27 / i.MX31 / i.MX5 rocessors.
  135. config NAND_MXS
  136. bool "MXS NAND support"
  137. depends on MX23 || MX28 || MX6 || MX7
  138. select SYS_NAND_SELF_INIT
  139. imply CMD_NAND
  140. select APBH_DMA
  141. select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
  142. select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
  143. help
  144. This enables NAND driver for the NAND flash controller on the
  145. MXS processors.
  146. if NAND_MXS
  147. config NAND_MXS_DT
  148. bool "Support MXS NAND controller as a DT device"
  149. depends on OF_CONTROL && MTD
  150. help
  151. Enable the driver for MXS NAND flash on platforms using
  152. device tree.
  153. config NAND_MXS_USE_MINIMUM_ECC
  154. bool "Use minimum ECC strength supported by the controller"
  155. default false
  156. endif
  157. config NAND_ZYNQ
  158. bool "Support for Zynq Nand controller"
  159. select SYS_NAND_SELF_INIT
  160. imply CMD_NAND
  161. help
  162. This enables Nand driver support for Nand flash controller
  163. found on Zynq SoC.
  164. config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  165. bool "Enable use of 1st stage bootloader timing for NAND"
  166. depends on NAND_ZYNQ
  167. help
  168. This flag prevent U-boot reconfigure NAND flash controller and reuse
  169. the NAND timing from 1st stage bootloader.
  170. comment "Generic NAND options"
  171. config SYS_NAND_BLOCK_SIZE
  172. hex "NAND chip eraseblock size"
  173. depends on ARCH_SUNXI
  174. help
  175. Number of data bytes in one eraseblock for the NAND chip on the
  176. board. This is the multiple of NAND_PAGE_SIZE and the number of
  177. pages.
  178. config SYS_NAND_PAGE_SIZE
  179. hex "NAND chip page size"
  180. depends on ARCH_SUNXI
  181. help
  182. Number of data bytes in one page for the NAND chip on the
  183. board, not including the OOB area.
  184. config SYS_NAND_OOBSIZE
  185. hex "NAND chip OOB size"
  186. depends on ARCH_SUNXI
  187. help
  188. Number of bytes in the Out-Of-Band area for the NAND chip on
  189. the board.
  190. # Enhance depends when converting drivers to Kconfig which use this config
  191. # option (mxc_nand, ndfc, omap_gpmc).
  192. config SYS_NAND_BUSWIDTH_16BIT
  193. bool "Use 16-bit NAND interface"
  194. depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
  195. help
  196. Indicates that NAND device has 16-bit wide data-bus. In absence of this
  197. config, bus-width of NAND device is assumed to be either 8-bit and later
  198. determined by reading ONFI params.
  199. Above config is useful when NAND device's bus-width information cannot
  200. be determined from on-chip ONFI params, like in following scenarios:
  201. - SPL boot does not support reading of ONFI parameters. This is done to
  202. keep SPL code foot-print small.
  203. - In current U-Boot flow using nand_init(), driver initialization
  204. happens in board_nand_init() which is called before any device probe
  205. (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
  206. not available while configuring controller. So a static CONFIG_NAND_xx
  207. is needed to know the device's bus-width in advance.
  208. if SPL
  209. config SYS_NAND_U_BOOT_LOCATIONS
  210. bool "Define U-boot binaries locations in NAND"
  211. help
  212. Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
  213. This option should not be enabled when compiling U-boot for boards
  214. defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
  215. file.
  216. config SYS_NAND_U_BOOT_OFFS
  217. hex "Location in NAND to read U-Boot from"
  218. default 0x800000 if NAND_SUNXI
  219. depends on SYS_NAND_U_BOOT_LOCATIONS
  220. help
  221. Set the offset from the start of the nand where u-boot should be
  222. loaded from.
  223. config SYS_NAND_U_BOOT_OFFS_REDUND
  224. hex "Location in NAND to read U-Boot from"
  225. default SYS_NAND_U_BOOT_OFFS
  226. depends on SYS_NAND_U_BOOT_LOCATIONS
  227. help
  228. Set the offset from the start of the nand where the redundant u-boot
  229. should be loaded from.
  230. config SPL_NAND_AM33XX_BCH
  231. bool "Enables SPL-NAND driver which supports ELM based"
  232. depends on NAND_OMAP_GPMC && !OMAP34XX
  233. default y
  234. help
  235. Hardware ECC correction. This is useful for platforms which have ELM
  236. hardware engine and use NAND boot mode.
  237. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  238. so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
  239. SPL-NAND driver with software ECC correction support.
  240. config SPL_NAND_DENALI
  241. bool "Support Denali NAND controller for SPL"
  242. help
  243. This is a small implementation of the Denali NAND controller
  244. for use on SPL.
  245. config SPL_NAND_SIMPLE
  246. bool "Use simple SPL NAND driver"
  247. depends on !SPL_NAND_AM33XX_BCH
  248. help
  249. Support for NAND boot using simple NAND drivers that
  250. expose the cmd_ctrl() interface.
  251. endif
  252. endif # if NAND