fm_eth.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __FM_ETH_H__
  6. #define __FM_ETH_H__
  7. #include <common.h>
  8. #include <phy.h>
  9. #include <asm/types.h>
  10. enum fm_port {
  11. FM1_DTSEC1,
  12. FM1_DTSEC2,
  13. FM1_DTSEC3,
  14. FM1_DTSEC4,
  15. FM1_DTSEC5,
  16. FM1_DTSEC6,
  17. FM1_DTSEC9,
  18. FM1_DTSEC10,
  19. FM1_10GEC1,
  20. FM1_10GEC2,
  21. FM1_10GEC3,
  22. FM1_10GEC4,
  23. FM2_DTSEC1,
  24. FM2_DTSEC2,
  25. FM2_DTSEC3,
  26. FM2_DTSEC4,
  27. FM2_DTSEC5,
  28. FM2_DTSEC6,
  29. FM2_DTSEC9,
  30. FM2_DTSEC10,
  31. FM2_10GEC1,
  32. FM2_10GEC2,
  33. NUM_FM_PORTS,
  34. };
  35. enum fm_eth_type {
  36. FM_ETH_1G_E,
  37. FM_ETH_10G_E,
  38. };
  39. #ifdef CONFIG_SYS_FMAN_V3
  40. #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
  41. #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
  42. #if (CONFIG_SYS_NUM_FMAN == 2)
  43. #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
  44. #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
  45. #endif
  46. #else
  47. #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
  48. #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
  49. #endif
  50. #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
  51. #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
  52. /* Fman ethernet info struct */
  53. #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
  54. .fm = idx, \
  55. .phy_regs = (void *)pregs, \
  56. .enet_if = PHY_INTERFACE_MODE_NONE, \
  57. #ifdef CONFIG_SYS_FMAN_V3
  58. #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
  59. { \
  60. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
  61. .index = idx, \
  62. .num = n - 1, \
  63. .type = FM_ETH_1G_E, \
  64. .port = FM##idx##_DTSEC##n, \
  65. .rx_port_id = RX_PORT_1G_BASE + n - 1, \
  66. .tx_port_id = TX_PORT_1G_BASE + n - 1, \
  67. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  68. offsetof(struct ccsr_fman, memac[n-1]),\
  69. }
  70. #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  71. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  72. { \
  73. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  74. .index = idx, \
  75. .num = n - 1, \
  76. .type = FM_ETH_10G_E, \
  77. .port = FM##idx##_10GEC##n, \
  78. .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
  79. .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
  80. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  81. offsetof(struct ccsr_fman, memac[n-1]),\
  82. }
  83. #else
  84. #if (CONFIG_SYS_NUM_FMAN == 2)
  85. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  86. { \
  87. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
  88. .index = idx, \
  89. .num = n - 1, \
  90. .type = FM_ETH_10G_E, \
  91. .port = FM##idx##_10GEC##n, \
  92. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  93. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  94. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  95. offsetof(struct ccsr_fman, memac[n-1+8]),\
  96. }
  97. #else
  98. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  99. { \
  100. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  101. .index = idx, \
  102. .num = n - 1, \
  103. .type = FM_ETH_10G_E, \
  104. .port = FM##idx##_10GEC##n, \
  105. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  106. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  107. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  108. offsetof(struct ccsr_fman, memac[n-1+8]),\
  109. }
  110. #endif
  111. #endif
  112. #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
  113. #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
  114. { \
  115. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  116. .index = idx, \
  117. .num = n - 1, \
  118. .type = FM_ETH_10G_E, \
  119. .port = FM##idx##_10GEC##n, \
  120. .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
  121. .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
  122. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  123. offsetof(struct ccsr_fman, memac[n-1-2]),\
  124. }
  125. #endif
  126. #else
  127. #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
  128. { \
  129. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
  130. .index = idx, \
  131. .num = n - 1, \
  132. .type = FM_ETH_1G_E, \
  133. .port = FM##idx##_DTSEC##n, \
  134. .rx_port_id = RX_PORT_1G_BASE + n - 1, \
  135. .tx_port_id = TX_PORT_1G_BASE + n - 1, \
  136. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  137. offsetof(struct ccsr_fman, mac_1g[n-1]),\
  138. }
  139. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  140. { \
  141. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  142. .index = idx, \
  143. .num = n - 1, \
  144. .type = FM_ETH_10G_E, \
  145. .port = FM##idx##_10GEC##n, \
  146. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  147. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  148. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  149. offsetof(struct ccsr_fman, mac_10g[n-1]),\
  150. }
  151. #endif
  152. struct fm_eth_info {
  153. u8 enabled;
  154. u8 fm;
  155. u8 num;
  156. u8 phy_addr;
  157. int index;
  158. u16 rx_port_id;
  159. u16 tx_port_id;
  160. enum fm_port port;
  161. enum fm_eth_type type;
  162. void *phy_regs;
  163. phy_interface_t enet_if;
  164. u32 compat_offset;
  165. struct mii_dev *bus;
  166. };
  167. struct tgec_mdio_info {
  168. struct tgec_mdio_controller *regs;
  169. char *name;
  170. };
  171. struct memac_mdio_info {
  172. struct memac_mdio_controller *regs;
  173. char *name;
  174. };
  175. int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
  176. int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
  177. int fm_standard_init(bd_t *bis);
  178. void fman_enet_init(void);
  179. void fdt_fixup_fman_ethernet(void *fdt);
  180. phy_interface_t fm_info_get_enet_if(enum fm_port port);
  181. void fm_info_set_phy_address(enum fm_port port, int address);
  182. int fm_info_get_phy_address(enum fm_port port);
  183. void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
  184. void fm_disable_port(enum fm_port port);
  185. void fm_enable_port(enum fm_port port);
  186. void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
  187. unsigned int port_num, int phy_base_addr);
  188. int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
  189. unsigned int port_num, unsigned regnum);
  190. #endif