xpedite517x.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009 Extreme Engineering Solutions, Inc.
  4. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite517x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5170"
  15. #define CONFIG_SYS_FORM_3U_VPX 1
  16. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  17. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  18. #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
  19. #define CONFIG_ALTIVEC 1
  20. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  21. #define CONFIG_PCIE1 1 /* PCIE controller 1 */
  22. #define CONFIG_PCIE2 1 /* PCIE controller 2 */
  23. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  24. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  25. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  26. /*
  27. * DDR config
  28. */
  29. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  30. #define CONFIG_DDR_SPD
  31. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  32. #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
  33. #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
  34. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  35. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  36. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  37. #define CONFIG_DDR_ECC
  38. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  39. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  40. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  41. #define CONFIG_VERY_BIG_RAM
  42. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  43. /*
  44. * virtual address to be used for temporary mappings. There
  45. * should be 128k free at this VA.
  46. */
  47. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  48. #ifndef __ASSEMBLY__
  49. extern unsigned long get_board_sys_clk(unsigned long dummy);
  50. #endif
  51. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
  52. /*
  53. * L2CR setup
  54. */
  55. #define CONFIG_SYS_L2
  56. #define L2_INIT 0
  57. #define L2_ENABLE (L2CR_L2E)
  58. /*
  59. * Base addresses -- Note these are effective addresses where the
  60. * actual resources get mapped (not physical addresses)
  61. */
  62. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  63. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  64. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  65. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  66. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  67. /*
  68. * Diagnostics
  69. */
  70. #define CONFIG_SYS_MEMTEST_START 0x10000000
  71. #define CONFIG_SYS_MEMTEST_END 0x20000000
  72. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
  73. CONFIG_SYS_POST_I2C)
  74. /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  75. #define I2C_ADDR_IGNORE_LIST {0x50}
  76. /*
  77. * Memory map
  78. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  79. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  80. * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
  81. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  82. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  83. * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  84. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  85. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  86. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  87. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  88. */
  89. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
  90. /*
  91. * NAND flash configuration
  92. */
  93. #define CONFIG_SYS_NAND_BASE 0xef800000
  94. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  95. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
  96. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  97. #define CONFIG_NAND_ACTL
  98. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
  99. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
  100. #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
  101. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  102. #define CONFIG_JFFS2_NAND
  103. /*
  104. * NOR flash configuration
  105. */
  106. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  107. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  108. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  109. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  110. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  111. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  112. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  113. #define CONFIG_FLASH_CFI_DRIVER
  114. #define CONFIG_SYS_FLASH_CFI
  115. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  116. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
  117. {0xf7f00000, 0xc0000} }
  118. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  119. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  120. /*
  121. * Chip select configuration
  122. */
  123. /* NOR Flash 0 on CS0 */
  124. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  125. BR_PS_16 |\
  126. BR_V)
  127. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
  128. OR_GPCM_CSNT |\
  129. OR_GPCM_XACS |\
  130. OR_GPCM_ACS_DIV2 |\
  131. OR_GPCM_SCY_8 |\
  132. OR_GPCM_TRLX |\
  133. OR_GPCM_EHTR |\
  134. OR_GPCM_EAD)
  135. /* NOR Flash 1 on CS1 */
  136. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
  137. BR_PS_16 |\
  138. BR_V)
  139. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  140. /* NAND flash on CS2 */
  141. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
  142. BR_PS_8 |\
  143. BR_V)
  144. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
  145. OR_GPCM_BCTLD |\
  146. OR_GPCM_CSNT |\
  147. OR_GPCM_ACS_DIV4 |\
  148. OR_GPCM_SCY_4 |\
  149. OR_GPCM_TRLX |\
  150. OR_GPCM_EHTR)
  151. /* Optional NAND flash on CS3 */
  152. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
  153. BR_PS_8 |\
  154. BR_V)
  155. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  156. /*
  157. * Use L1 as initial stack
  158. */
  159. #define CONFIG_SYS_INIT_RAM_LOCK 1
  160. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  161. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  162. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  163. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  164. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  165. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  166. /*
  167. * Serial Port
  168. */
  169. #define CONFIG_SYS_NS16550_SERIAL
  170. #define CONFIG_SYS_NS16550_REG_SIZE 1
  171. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  172. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  173. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  174. #define CONFIG_SYS_BAUDRATE_TABLE \
  175. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  176. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  177. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  178. /*
  179. * I2C
  180. */
  181. #define CONFIG_SYS_I2C
  182. #define CONFIG_SYS_I2C_FSL
  183. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  184. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  185. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  186. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  187. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  188. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  189. /* PEX8518 slave I2C interface */
  190. #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
  191. /* I2C DS1631 temperature sensor */
  192. #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
  193. /* I2C EEPROM - AT24C128B */
  194. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  195. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  196. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  197. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  198. /* I2C RTC */
  199. #define CONFIG_RTC_M41T11 1
  200. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  201. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  202. /* GPIO */
  203. #define CONFIG_PCA953X
  204. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  205. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  206. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  207. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  208. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  209. #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
  210. /*
  211. * PU = pulled high, PD = pulled low
  212. * I = input, O = output, IO = input/output
  213. */
  214. /* PCA9557 @ 0x18*/
  215. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  216. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
  217. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  218. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
  219. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  220. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
  221. /* PCA9557 @ 0x1c*/
  222. #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
  223. #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
  224. #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
  225. #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
  226. #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
  227. #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
  228. #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
  229. #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
  230. /* PCA9557 @ 0x1e*/
  231. #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
  232. #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
  233. #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
  234. #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
  235. #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
  236. #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
  237. #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
  238. /* PCA9557 @ 0x1f */
  239. #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
  240. #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
  241. #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
  242. #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
  243. /*
  244. * General PCI
  245. * Memory space is mapped 1-1, but I/O space must start from 0.
  246. */
  247. /* PCIE1 - PEX8518 */
  248. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  249. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  250. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  251. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  252. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  253. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  254. /* PCIE2 - VPX P1 */
  255. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  256. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  257. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  258. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  259. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
  260. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
  261. /*
  262. * Networking options
  263. */
  264. #define CONFIG_MII 1 /* MII PHY management */
  265. #define CONFIG_ETHPRIME "eTSEC1"
  266. #define CONFIG_TSEC1 1
  267. #define CONFIG_TSEC1_NAME "eTSEC1"
  268. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  269. #define TSEC1_PHY_ADDR 1
  270. #define TSEC1_PHYIDX 0
  271. #define CONFIG_HAS_ETH0
  272. #define CONFIG_TSEC2 1
  273. #define CONFIG_TSEC2_NAME "eTSEC2"
  274. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  275. #define TSEC2_PHY_ADDR 2
  276. #define TSEC2_PHYIDX 0
  277. #define CONFIG_HAS_ETH1
  278. /*
  279. * BAT mappings
  280. */
  281. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  282. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  283. BATL_PP_RW |\
  284. BATL_CACHEINHIBIT |\
  285. BATL_GUARDEDSTORAGE)
  286. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
  287. BATU_BL_1M |\
  288. BATU_VS |\
  289. BATU_VP)
  290. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  291. BATL_PP_RW |\
  292. BATL_CACHEINHIBIT)
  293. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  294. #endif
  295. /*
  296. * BAT0 2G Cacheable, non-guarded
  297. * 0x0000_0000 2G DDR
  298. */
  299. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  300. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  301. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  302. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  303. /*
  304. * BAT1 1G Cache-inhibited, guarded
  305. * 0x8000_0000 1G PCI-Express 1 Memory
  306. */
  307. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  308. BATL_PP_RW |\
  309. BATL_CACHEINHIBIT |\
  310. BATL_GUARDEDSTORAGE)
  311. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
  312. BATU_BL_1G |\
  313. BATU_VS |\
  314. BATU_VP)
  315. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  316. BATL_PP_RW |\
  317. BATL_CACHEINHIBIT)
  318. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  319. /*
  320. * BAT2 512M Cache-inhibited, guarded
  321. * 0xc000_0000 512M PCI-Express 2 Memory
  322. */
  323. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  324. BATL_PP_RW |\
  325. BATL_CACHEINHIBIT |\
  326. BATL_GUARDEDSTORAGE)
  327. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
  328. BATU_BL_512M |\
  329. BATU_VS |\
  330. BATU_VP)
  331. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  332. BATL_PP_RW |\
  333. BATL_CACHEINHIBIT)
  334. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  335. /*
  336. * BAT3 1M Cache-inhibited, guarded
  337. * 0xe000_0000 1M CCSR
  338. */
  339. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
  340. BATL_PP_RW |\
  341. BATL_CACHEINHIBIT |\
  342. BATL_GUARDEDSTORAGE)
  343. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
  344. BATU_BL_1M |\
  345. BATU_VS |\
  346. BATU_VP)
  347. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
  348. BATL_PP_RW |\
  349. BATL_CACHEINHIBIT)
  350. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  351. /*
  352. * BAT4 32M Cache-inhibited, guarded
  353. * 0xe200_0000 16M PCI-Express 1 I/O
  354. * 0xe300_0000 16M PCI-Express 2 I/0
  355. */
  356. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  357. BATL_PP_RW |\
  358. BATL_CACHEINHIBIT |\
  359. BATL_GUARDEDSTORAGE)
  360. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
  361. BATU_BL_32M |\
  362. BATU_VS |\
  363. BATU_VP)
  364. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  365. BATL_PP_RW |\
  366. BATL_CACHEINHIBIT)
  367. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  368. /*
  369. * BAT5 128K Cacheable, non-guarded
  370. * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
  371. */
  372. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
  373. BATL_PP_RW |\
  374. BATL_MEMCOHERENCE)
  375. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
  376. BATU_BL_128K |\
  377. BATU_VS |\
  378. BATU_VP)
  379. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  380. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  381. /*
  382. * BAT6 256M Cache-inhibited, guarded
  383. * 0xf000_0000 256M FLASH
  384. */
  385. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
  386. BATL_PP_RW |\
  387. BATL_CACHEINHIBIT |\
  388. BATL_GUARDEDSTORAGE)
  389. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
  390. BATU_BL_256M |\
  391. BATU_VS |\
  392. BATU_VP)
  393. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
  394. BATL_PP_RW |\
  395. BATL_MEMCOHERENCE)
  396. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  397. /* Map the last 1M of flash where we're running from reset */
  398. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  399. BATL_PP_RW |\
  400. BATL_CACHEINHIBIT |\
  401. BATL_GUARDEDSTORAGE)
  402. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
  403. BATU_BL_1M |\
  404. BATU_VS |\
  405. BATU_VP)
  406. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  407. BATL_PP_RW |\
  408. BATL_MEMCOHERENCE)
  409. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  410. /*
  411. * BAT7 64M Cache-inhibited, guarded
  412. * 0xe800_0000 64K NAND FLASH
  413. * 0xe804_0000 128K DUART Registers
  414. */
  415. #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
  416. BATL_PP_RW |\
  417. BATL_CACHEINHIBIT |\
  418. BATL_GUARDEDSTORAGE)
  419. #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
  420. BATU_BL_512K |\
  421. BATU_VS |\
  422. BATU_VP)
  423. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
  424. BATL_PP_RW |\
  425. BATL_CACHEINHIBIT)
  426. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  427. /*
  428. * Miscellaneous configurable options
  429. */
  430. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  431. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  432. #define CONFIG_PREBOOT /* enable preboot variable */
  433. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  434. /*
  435. * For booting Linux, the board info and command line data
  436. * have to be in the first 16 MB of memory, since this is
  437. * the maximum mapped by the Linux kernel during initialization.
  438. */
  439. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  440. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  441. /*
  442. * Environment Configuration
  443. */
  444. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  445. #define CONFIG_ENV_SIZE 0x8000
  446. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  447. /*
  448. * Flash memory map:
  449. * fffc0000 - ffffffff Pri FDT (256KB)
  450. * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
  451. * fff00000 - fff7ffff Pri U-Boot (512 KB)
  452. * fef00000 - ffefffff Pri OS image (16MB)
  453. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  454. *
  455. * f7fc0000 - f7ffffff Sec FDT (256KB)
  456. * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
  457. * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
  458. * f6f00000 - f7efffff Sec OS image (16MB)
  459. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  460. */
  461. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
  462. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
  463. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
  464. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
  465. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  466. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  467. #define CONFIG_PROG_UBOOT1 \
  468. "$download_cmd $loadaddr $ubootfile; " \
  469. "if test $? -eq 0; then " \
  470. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  471. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  472. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  473. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  474. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  475. "if test $? -ne 0; then " \
  476. "echo PROGRAM FAILED; " \
  477. "else; " \
  478. "echo PROGRAM SUCCEEDED; " \
  479. "fi; " \
  480. "else; " \
  481. "echo DOWNLOAD FAILED; " \
  482. "fi;"
  483. #define CONFIG_PROG_UBOOT2 \
  484. "$download_cmd $loadaddr $ubootfile; " \
  485. "if test $? -eq 0; then " \
  486. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  487. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  488. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  489. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  490. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  491. "if test $? -ne 0; then " \
  492. "echo PROGRAM FAILED; " \
  493. "else; " \
  494. "echo PROGRAM SUCCEEDED; " \
  495. "fi; " \
  496. "else; " \
  497. "echo DOWNLOAD FAILED; " \
  498. "fi;"
  499. #define CONFIG_BOOT_OS_NET \
  500. "$download_cmd $osaddr $osfile; " \
  501. "if test $? -eq 0; then " \
  502. "if test -n $fdtaddr; then " \
  503. "$download_cmd $fdtaddr $fdtfile; " \
  504. "if test $? -eq 0; then " \
  505. "bootm $osaddr - $fdtaddr; " \
  506. "else; " \
  507. "echo FDT DOWNLOAD FAILED; " \
  508. "fi; " \
  509. "else; " \
  510. "bootm $osaddr; " \
  511. "fi; " \
  512. "else; " \
  513. "echo OS DOWNLOAD FAILED; " \
  514. "fi;"
  515. #define CONFIG_PROG_OS1 \
  516. "$download_cmd $osaddr $osfile; " \
  517. "if test $? -eq 0; then " \
  518. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  519. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  520. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  521. "if test $? -ne 0; then " \
  522. "echo OS PROGRAM FAILED; " \
  523. "else; " \
  524. "echo OS PROGRAM SUCCEEDED; " \
  525. "fi; " \
  526. "else; " \
  527. "echo OS DOWNLOAD FAILED; " \
  528. "fi;"
  529. #define CONFIG_PROG_OS2 \
  530. "$download_cmd $osaddr $osfile; " \
  531. "if test $? -eq 0; then " \
  532. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  533. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  534. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  535. "if test $? -ne 0; then " \
  536. "echo OS PROGRAM FAILED; " \
  537. "else; " \
  538. "echo OS PROGRAM SUCCEEDED; " \
  539. "fi; " \
  540. "else; " \
  541. "echo OS DOWNLOAD FAILED; " \
  542. "fi;"
  543. #define CONFIG_PROG_FDT1 \
  544. "$download_cmd $fdtaddr $fdtfile; " \
  545. "if test $? -eq 0; then " \
  546. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  547. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  548. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  549. "if test $? -ne 0; then " \
  550. "echo FDT PROGRAM FAILED; " \
  551. "else; " \
  552. "echo FDT PROGRAM SUCCEEDED; " \
  553. "fi; " \
  554. "else; " \
  555. "echo FDT DOWNLOAD FAILED; " \
  556. "fi;"
  557. #define CONFIG_PROG_FDT2 \
  558. "$download_cmd $fdtaddr $fdtfile; " \
  559. "if test $? -eq 0; then " \
  560. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  561. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  562. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  563. "if test $? -ne 0; then " \
  564. "echo FDT PROGRAM FAILED; " \
  565. "else; " \
  566. "echo FDT PROGRAM SUCCEEDED; " \
  567. "fi; " \
  568. "else; " \
  569. "echo FDT DOWNLOAD FAILED; " \
  570. "fi;"
  571. #define CONFIG_EXTRA_ENV_SETTINGS \
  572. "autoload=yes\0" \
  573. "download_cmd=tftp\0" \
  574. "console_args=console=ttyS0,115200\0" \
  575. "root_args=root=/dev/nfs rw\0" \
  576. "misc_args=ip=on\0" \
  577. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  578. "bootfile=/home/user/file\0" \
  579. "osfile=/home/user/board.uImage\0" \
  580. "fdtfile=/home/user/board.dtb\0" \
  581. "ubootfile=/home/user/u-boot.bin\0" \
  582. "fdtaddr=0x1e00000\0" \
  583. "osaddr=0x1000000\0" \
  584. "loadaddr=0x1000000\0" \
  585. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  586. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  587. "prog_os1="CONFIG_PROG_OS1"\0" \
  588. "prog_os2="CONFIG_PROG_OS2"\0" \
  589. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  590. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  591. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  592. "bootcmd_flash1=run set_bootargs; " \
  593. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  594. "bootcmd_flash2=run set_bootargs; " \
  595. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  596. "bootcmd=run bootcmd_flash1\0"
  597. #endif /* __CONFIG_H */