tricorder.h 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Texas Instruments.
  5. * Richard Woodruff <r-woodruff2@ti.com>
  6. * Syed Mohammed Khasim <x0khasim@ti.com>
  7. *
  8. * (C) Copyright 2012
  9. * Corscience GmbH & Co. KG
  10. * Thomas Weber <weber@corscience.de>
  11. *
  12. * Configuration settings for the Tricorder board.
  13. */
  14. #ifndef __CONFIG_H
  15. #define __CONFIG_H
  16. #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
  17. /*
  18. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  19. * 64 bytes before this address should be set aside for u-boot.img's
  20. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  21. * other needs.
  22. */
  23. #include <asm/arch/cpu.h> /* get chip and board defs */
  24. #include <asm/arch/omap.h>
  25. /* Clock Defines */
  26. #define V_OSCK 26000000 /* Clock output from T2 */
  27. #define V_SCLK (V_OSCK >> 1)
  28. #define CONFIG_MISC_INIT_R
  29. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  30. #define CONFIG_SETUP_MEMORY_TAGS
  31. #define CONFIG_INITRD_TAG
  32. #define CONFIG_REVISION_TAG
  33. /* Size of malloc() pool */
  34. #define CONFIG_SYS_MALLOC_LEN (1024*1024)
  35. /* Hardware drivers */
  36. /* NS16550 Configuration */
  37. #define CONFIG_SYS_NS16550_SERIAL
  38. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  39. #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  40. /* select serial console configuration */
  41. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  42. #define CONFIG_SERIAL3 3
  43. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  44. 115200}
  45. /* I2C */
  46. #define CONFIG_SYS_I2C
  47. /* EEPROM */
  48. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  49. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  50. /* TWL4030 */
  51. #define CONFIG_TWL4030_LED
  52. /* Board NAND Info */
  53. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  54. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  55. /* to access nand */
  56. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  57. /* to access nand at */
  58. /* CS0 */
  59. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  60. /* devices */
  61. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  62. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  63. /* needed for ubi */
  64. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  65. #define CONFIG_MTD_PARTITIONS
  66. /* Environment information (this is the common part) */
  67. /* hang() the board on panic() */
  68. /* environment placement (for NAND), is different for FLASHCARD but does not
  69. * harm there */
  70. #define CONFIG_ENV_OFFSET 0x120000 /* env start */
  71. #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
  72. #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
  73. #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
  74. /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
  75. * value can not be used here! */
  76. #define CONFIG_LOADADDR 0x82000000
  77. #define CONFIG_COMMON_ENV_SETTINGS \
  78. "console=ttyO2,115200n8\0" \
  79. "mmcdev=0\0" \
  80. "vram=3M\0" \
  81. "defaultdisplay=lcd\0" \
  82. "kernelopts=mtdoops.mtddev=3\0" \
  83. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  84. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  85. "commonargs=" \
  86. "setenv bootargs console=${console} " \
  87. "${mtdparts} " \
  88. "${kernelopts} " \
  89. "vt.global_cursor_default=0 " \
  90. "vram=${vram} " \
  91. "omapdss.def_disp=${defaultdisplay}\0"
  92. #define CONFIG_BOOTCOMMAND "run autoboot"
  93. /* specific environment settings for different use cases
  94. * FLASHCARD: used to run a rdimage from sdcard to program the device
  95. * 'NORMAL': used to boot kernel from sdcard, nand, ...
  96. *
  97. * The main aim for the FLASHCARD skin is to have an embedded environment
  98. * which will not be influenced by any data already on the device.
  99. */
  100. #ifdef CONFIG_FLASHCARD
  101. /* the rdaddr is 16 MiB before the loadaddr */
  102. #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
  103. #define CONFIG_EXTRA_ENV_SETTINGS \
  104. CONFIG_COMMON_ENV_SETTINGS \
  105. CONFIG_ENV_RDADDR \
  106. "autoboot=" \
  107. "run commonargs; " \
  108. "setenv bootargs ${bootargs} " \
  109. "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
  110. "rdinit=/sbin/init; " \
  111. "mmc dev ${mmcdev}; mmc rescan; " \
  112. "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
  113. "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
  114. "bootm ${loadaddr} ${rdaddr}\0"
  115. #else /* CONFIG_FLASHCARD */
  116. #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
  117. #define CONFIG_EXTRA_ENV_SETTINGS \
  118. CONFIG_COMMON_ENV_SETTINGS \
  119. "mmcargs=" \
  120. "run commonargs; " \
  121. "setenv bootargs ${bootargs} " \
  122. "root=/dev/mmcblk0p2 " \
  123. "rootwait " \
  124. "rw\0" \
  125. "nandargs=" \
  126. "run commonargs; " \
  127. "setenv bootargs ${bootargs} " \
  128. "root=ubi0:root " \
  129. "ubi.mtd=7 " \
  130. "rootfstype=ubifs " \
  131. "ro\0" \
  132. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  133. "bootscript=echo Running bootscript from mmc ...; " \
  134. "source ${loadaddr}\0" \
  135. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  136. "mmcboot=echo Booting from mmc ...; " \
  137. "run mmcargs; " \
  138. "bootm ${loadaddr}\0" \
  139. "loaduimage_ubi=ubi part ubi; " \
  140. "ubifsmount ubi:root; " \
  141. "ubifsload ${loadaddr} /boot/uImage\0" \
  142. "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
  143. "nandboot=echo Booting from nand ...; " \
  144. "run nandargs; " \
  145. "run loaduimage_nand; " \
  146. "bootm ${loadaddr}\0" \
  147. "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
  148. "if run loadbootscript; then " \
  149. "run bootscript; " \
  150. "else " \
  151. "if run loaduimage; then " \
  152. "run mmcboot; " \
  153. "else run nandboot; " \
  154. "fi; " \
  155. "fi; " \
  156. "else run nandboot; fi\0"
  157. #endif /* CONFIG_FLASHCARD */
  158. /* Miscellaneous configurable options */
  159. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  160. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
  161. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  162. 0x07000000) /* 112 MB */
  163. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
  164. /*
  165. * OMAP3 has 12 GP timers, they can be driven by the system clock
  166. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  167. * This rate is divided by a local divisor.
  168. */
  169. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  170. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  171. /* Physical Memory Map */
  172. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  173. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  174. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  175. /* NAND and environment organization */
  176. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  177. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  178. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  179. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  180. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  181. CONFIG_SYS_INIT_RAM_SIZE - \
  182. GENERATED_GBL_DATA_SIZE)
  183. /* SRAM config */
  184. #define CONFIG_SYS_SRAM_START 0x40200000
  185. #define CONFIG_SYS_SRAM_SIZE 0x10000
  186. /* Defines for SPL */
  187. #define CONFIG_SPL_NAND_BASE
  188. #define CONFIG_SPL_NAND_DRIVERS
  189. #define CONFIG_SPL_NAND_ECC
  190. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  191. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  192. #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
  193. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  194. CONFIG_SPL_TEXT_BASE)
  195. #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
  196. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  197. /* NAND boot config */
  198. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  199. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  200. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  201. #define CONFIG_SYS_NAND_OOBSIZE 64
  202. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  203. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  204. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
  205. 13, 14, 16, 17, 18, 19, 20, 21, 22, \
  206. 23, 24, 25, 26, 27, 28, 30, 31, 32, \
  207. 33, 34, 35, 36, 37, 38, 39, 40, 41, \
  208. 42, 44, 45, 46, 47, 48, 49, 50, 51, \
  209. 52, 53, 54, 55, 56}
  210. #define CONFIG_SYS_NAND_ECCSIZE 512
  211. #define CONFIG_SYS_NAND_ECCBYTES 13
  212. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
  213. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  214. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
  215. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
  216. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  217. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
  218. #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
  219. #endif /* __CONFIG_H */