theadorable.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #ifndef _CONFIG_THEADORABLE_H
  6. #define _CONFIG_THEADORABLE_H
  7. /*
  8. * High Level Configuration Options (easy to change)
  9. */
  10. /*
  11. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  12. * for DDR ECC byte filling in the SPL before loading the main
  13. * U-Boot into it.
  14. */
  15. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  16. /*
  17. * Commands configuration
  18. */
  19. /*
  20. * The debugging version enables USB support via defconfig.
  21. * This version should also enable all other non-production
  22. * interfaces / features.
  23. */
  24. /* I2C */
  25. #define CONFIG_SYS_I2C
  26. #define CONFIG_SYS_I2C_MVTWSI
  27. #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
  28. #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
  29. #define CONFIG_SYS_I2C_SLAVE 0x0
  30. #define CONFIG_SYS_I2C_SPEED 100000
  31. /* USB/EHCI configuration */
  32. #define CONFIG_EHCI_IS_TDI
  33. #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  34. /* SPI NOR flash default params, used by sf commands */
  35. #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
  36. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
  37. /* Environment in SPI NOR flash */
  38. #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
  39. #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
  40. #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
  41. #define CONFIG_ENV_OVERWRITE
  42. #define CONFIG_PHY_MARVELL /* there is a marvell phy */
  43. #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
  44. #define CONFIG_PREBOOT
  45. /* Keep device tree and initrd in lower memory so the kernel can access them */
  46. #define CONFIG_EXTRA_ENV_SETTINGS \
  47. "fdt_high=0x10000000\0" \
  48. "initrd_high=0x10000000\0"
  49. /* SATA support */
  50. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  51. #define CONFIG_LBA48
  52. /* PCIe support */
  53. #ifdef CONFIG_CMD_PCI
  54. #ifndef CONFIG_SPL_BUILD
  55. #define CONFIG_PCI_MVEBU
  56. #endif
  57. #endif
  58. /* Enable LCD and reserve 512KB from top of memory*/
  59. #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
  60. /* FPGA programming support */
  61. #define CONFIG_FPGA_STRATIX_V
  62. /*
  63. * Bootcounter
  64. */
  65. /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
  66. #define BOOTCOUNT_ADDR 0x1000
  67. /*
  68. * mv-common.h should be defined after CMD configs since it used them
  69. * to enable certain macros
  70. */
  71. #include "mv-common.h"
  72. /*
  73. * Memory layout while starting into the bin_hdr via the
  74. * BootROM:
  75. *
  76. * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
  77. * 0x4000.4030 bin_hdr start address
  78. * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
  79. * 0x4007.fffc BootROM stack top
  80. *
  81. * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  82. * L2 cache thus cannot be used.
  83. */
  84. /* SPL */
  85. /* Defines for SPL */
  86. #define CONFIG_SPL_TEXT_BASE 0x40004030
  87. #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
  88. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
  89. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  90. #ifdef CONFIG_SPL_BUILD
  91. #define CONFIG_SYS_MALLOC_SIMPLE
  92. #endif
  93. #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
  94. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  95. /* SPL related SPI defines */
  96. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
  97. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
  98. /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  99. #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
  100. #endif /* _CONFIG_THEADORABLE_H */