tao3530.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the TechNexion TAO-3530 SOM
  4. * equipped on Thunder baseboard.
  5. *
  6. * Edward Lin <linuxfae@technexion.com>
  7. * Tapani Utriainen <linuxfae@technexion.com>
  8. *
  9. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #include <asm/arch/cpu.h> /* get chip and board defs */
  17. #include <asm/arch/omap.h>
  18. /* Clock Defines */
  19. #define V_OSCK 26000000 /* Clock output from T2 */
  20. #define V_SCLK (V_OSCK >> 1)
  21. #define CONFIG_MISC_INIT_R
  22. #define CONFIG_CMDLINE_TAG
  23. #define CONFIG_SETUP_MEMORY_TAGS
  24. #define CONFIG_INITRD_TAG
  25. #define CONFIG_REVISION_TAG
  26. /*
  27. * Size of malloc() pool
  28. */
  29. #define CONFIG_SYS_MALLOC_LEN (4 << 20)
  30. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
  31. /*
  32. * Hardware drivers
  33. */
  34. /*
  35. * NS16550 Configuration
  36. */
  37. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  38. #define CONFIG_SYS_NS16550_SERIAL
  39. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  40. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  41. /*
  42. * select serial console configuration
  43. */
  44. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  45. /* allow to overwrite serial and ethaddr */
  46. #define CONFIG_ENV_OVERWRITE
  47. /* commands to include */
  48. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  49. #define CONFIG_SYS_I2C
  50. #define CONFIG_I2C_MULTI_BUS
  51. /*
  52. * TWL4030
  53. */
  54. #define CONFIG_TWL4030_LED
  55. /*
  56. * Board NAND Info.
  57. */
  58. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  59. /* to access nand */
  60. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  61. /* to access nand at */
  62. /* CS0 */
  63. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  64. /* devices */
  65. /* Environment information */
  66. #define CONFIG_EXTRA_ENV_SETTINGS \
  67. "loadaddr=0x82000000\0" \
  68. "console=ttyO2,115200n8\0" \
  69. "mpurate=600\0" \
  70. "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
  71. "tv_mode=omapfb.mode=tv:ntsc\0" \
  72. "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
  73. "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
  74. "extra_options= \0" \
  75. "mmcdev=0\0" \
  76. "mmcroot=/dev/mmcblk0p2 rw\0" \
  77. "mmcrootfstype=ext3 rootwait\0" \
  78. "nandroot=ubi0:rootfs ubi.mtd=4\0" \
  79. "nandrootfstype=ubifs\0" \
  80. "mmcargs=setenv bootargs console=${console} " \
  81. "mpurate=${mpurate} " \
  82. "${video_mode} " \
  83. "root=${mmcroot} " \
  84. "rootfstype=${mmcrootfstype} " \
  85. "${extra_options}\0" \
  86. "nandargs=setenv bootargs console=${console} " \
  87. "mpurate=${mpurate} " \
  88. "${video_mode} " \
  89. "${network_setting} " \
  90. "root=${nandroot} " \
  91. "rootfstype=${nandrootfstype} "\
  92. "${extra_options}\0" \
  93. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  94. "bootscript=echo Running bootscript from mmc ...; " \
  95. "source ${loadaddr}\0" \
  96. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  97. "mmcboot=echo Booting from mmc ...; " \
  98. "run mmcargs; " \
  99. "bootm ${loadaddr}\0" \
  100. "nandboot=echo Booting from nand ...; " \
  101. "run nandargs; " \
  102. "nand read ${loadaddr} 280000 400000; " \
  103. "bootm ${loadaddr}\0" \
  104. #define CONFIG_BOOTCOMMAND \
  105. "if mmc rescan ${mmcdev}; then " \
  106. "if run loadbootscript; then " \
  107. "run bootscript; " \
  108. "else " \
  109. "if run loaduimage; then " \
  110. "run mmcboot; " \
  111. "else run nandboot; " \
  112. "fi; " \
  113. "fi; " \
  114. "else run nandboot; fi"
  115. /*
  116. * Miscellaneous configurable options
  117. */
  118. /* turn on command-line edit/hist/auto */
  119. #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
  120. /* defaults */
  121. #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
  122. #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
  123. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  124. /* load address */
  125. /*
  126. * OMAP3 has 12 GP timers, they can be driven by the system clock
  127. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  128. * This rate is divided by a local divisor.
  129. */
  130. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  131. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  132. /*
  133. * Physical Memory Map
  134. */
  135. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  136. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  137. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  138. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  139. /*
  140. * FLASH and environment organization
  141. */
  142. /* **** PISMO SUPPORT *** */
  143. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  144. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  145. /* Monitor at start of flash */
  146. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  147. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  148. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  149. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
  150. #define CONFIG_ENV_OFFSET 0x260000
  151. #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
  152. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  153. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  154. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  155. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  156. CONFIG_SYS_INIT_RAM_SIZE - \
  157. GENERATED_GBL_DATA_SIZE)
  158. /*
  159. * USB
  160. *
  161. * Currently only EHCI is enabled, the MUSB OTG controller
  162. * is not enabled.
  163. */
  164. /* USB EHCI */
  165. #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
  166. /* Defines for SPL */
  167. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  168. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  169. #define CONFIG_SPL_NAND_BASE
  170. #define CONFIG_SPL_NAND_DRIVERS
  171. #define CONFIG_SPL_NAND_ECC
  172. /* NAND boot config */
  173. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  174. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  175. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  176. #define CONFIG_SYS_NAND_OOBSIZE 64
  177. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  178. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  179. /*
  180. * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
  181. * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
  182. */
  183. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  184. 10, 11, 12, 13 }
  185. #define CONFIG_SYS_NAND_ECCSIZE 512
  186. #define CONFIG_SYS_NAND_ECCBYTES 3
  187. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  188. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  189. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  190. #define CONFIG_SPL_TEXT_BASE 0x40200800
  191. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  192. CONFIG_SPL_TEXT_BASE)
  193. /*
  194. * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
  195. * older x-loader implementations. And move the BSS area so that it
  196. * doesn't overlap with TEXT_BASE.
  197. */
  198. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  199. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  200. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  201. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  202. #endif /* __CONFIG_H */