t4qds.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * Corenet DS style board configuration file
  7. */
  8. #ifndef __T4QDS_H
  9. #define __T4QDS_H
  10. /* High Level Configuration Options */
  11. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  12. #define CONFIG_MP /* support multiple processors */
  13. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  15. #endif
  16. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  17. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  18. #define CONFIG_PCIE1 /* PCIE controller 1 */
  19. #define CONFIG_PCIE2 /* PCIE controller 2 */
  20. #define CONFIG_PCIE3 /* PCIE controller 3 */
  21. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  22. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  23. #define CONFIG_SYS_SRIO
  24. #define CONFIG_SRIO1 /* SRIO port 1 */
  25. #define CONFIG_SRIO2 /* SRIO port 2 */
  26. #define CONFIG_ENV_OVERWRITE
  27. /*
  28. * These can be toggled for performance analysis, otherwise use default.
  29. */
  30. #define CONFIG_SYS_CACHE_STASHING
  31. #define CONFIG_BTB /* toggle branch predition */
  32. #ifdef CONFIG_DDR_ECC
  33. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  35. #endif
  36. #define CONFIG_ENABLE_36BIT_PHYS
  37. #define CONFIG_ADDR_MAP
  38. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  39. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  40. #define CONFIG_SYS_MEMTEST_END 0x00400000
  41. /*
  42. * Config the L3 Cache as L3 SRAM
  43. */
  44. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  45. #define CONFIG_SYS_L3_SIZE (512 << 10)
  46. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  47. #ifdef CONFIG_RAMBOOT_PBL
  48. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  49. #endif
  50. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  51. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  52. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  53. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  54. #define CONFIG_SYS_DCSRBAR 0xf0000000
  55. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  56. /*
  57. * DDR Setup
  58. */
  59. #define CONFIG_VERY_BIG_RAM
  60. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  61. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  62. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  63. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  64. #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  65. #define CONFIG_DDR_SPD
  66. /*
  67. * IFC Definitions
  68. */
  69. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  70. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  71. #ifdef CONFIG_SPL_BUILD
  72. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  73. #else
  74. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  75. #endif
  76. #define CONFIG_MISC_INIT_R
  77. #define CONFIG_HWCONFIG
  78. /* define to use L1 as initial stack */
  79. #define CONFIG_L1_INIT_RAM
  80. #define CONFIG_SYS_INIT_RAM_LOCK
  81. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  82. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  83. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  84. /* The assembler doesn't like typecast */
  85. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  86. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  87. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  88. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  89. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  90. GENERATED_GBL_DATA_SIZE)
  91. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  92. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  93. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  94. /* Serial Port - controlled on board with jumper J8
  95. * open - index 2
  96. * shorted - index 1
  97. */
  98. #define CONFIG_SYS_NS16550_SERIAL
  99. #define CONFIG_SYS_NS16550_REG_SIZE 1
  100. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  101. #define CONFIG_SYS_BAUDRATE_TABLE \
  102. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  103. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  104. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  105. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  106. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  107. /* I2C */
  108. #define CONFIG_SYS_I2C
  109. #define CONFIG_SYS_I2C_FSL
  110. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  111. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  112. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  113. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  114. /*
  115. * RapidIO
  116. */
  117. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  118. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  119. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  120. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  121. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  122. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  123. /*
  124. * General PCI
  125. * Memory space is mapped 1-1, but I/O space must start from 0.
  126. */
  127. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  128. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  129. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  130. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  131. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  132. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  133. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  134. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  135. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  136. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  137. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  138. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  139. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  140. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  141. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  142. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  143. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  144. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  145. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  146. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  147. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  148. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  149. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  150. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  151. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  152. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  153. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  154. /* controller 4, Base address 203000 */
  155. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  156. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  157. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  158. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  159. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  160. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  161. #ifdef CONFIG_PCI
  162. #define CONFIG_PCI_INDIRECT_BRIDGE
  163. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  164. #endif /* CONFIG_PCI */
  165. /* SATA */
  166. #ifdef CONFIG_FSL_SATA_V2
  167. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  168. #define CONFIG_SATA1
  169. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  170. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  171. #define CONFIG_SATA2
  172. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  173. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  174. #define CONFIG_LBA48
  175. #endif
  176. #ifdef CONFIG_FMAN_ENET
  177. #define CONFIG_MII /* MII PHY management */
  178. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  179. #endif
  180. /*
  181. * Environment
  182. */
  183. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  184. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  185. /*
  186. * Command line configuration.
  187. */
  188. /*
  189. * Miscellaneous configurable options
  190. */
  191. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  192. /*
  193. * For booting Linux, the board info and command line data
  194. * have to be in the first 64 MB of memory, since this is
  195. * the maximum mapped by the Linux kernel during initialization.
  196. */
  197. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  198. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  199. #ifdef CONFIG_CMD_KGDB
  200. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  201. #endif
  202. /*
  203. * Environment Configuration
  204. */
  205. #define CONFIG_ROOTPATH "/opt/nfsroot"
  206. #define CONFIG_BOOTFILE "uImage"
  207. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  208. /* default location for tftp and bootm */
  209. #define CONFIG_LOADADDR 1000000
  210. #define CONFIG_HVBOOT \
  211. "setenv bootargs config-addr=0x60000000; " \
  212. "bootm 0x01000000 - 0x00f00000"
  213. #endif /* __CONFIG_H */