strider.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. *
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_E300 1 /* E300 family */
  13. #define CONFIG_MPC83xx 1 /* MPC83xx family */
  14. #define CONFIG_MPC830x 1 /* MPC830x family */
  15. #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
  16. #define CONFIG_STRIDER 1 /* STRIDER board specific */
  17. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18. /*
  19. * System Clock Setup
  20. */
  21. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  22. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  23. /*
  24. * Hardware Reset Configuration Word
  25. * if CLKIN is 66.66MHz, then
  26. * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  27. * We choose the A type silicon as default, so the core is 400Mhz.
  28. */
  29. #define CONFIG_SYS_HRCW_LOW (\
  30. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  31. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  32. HRCWL_SVCOD_DIV_2 |\
  33. HRCWL_CSB_TO_CLKIN_4X1 |\
  34. HRCWL_CORE_TO_CSB_3X1)
  35. /*
  36. * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  37. * in 8308's HRCWH according to the manual, but original Freescale's
  38. * code has them and I've expirienced some problems using the board
  39. * with BDI3000 attached when I've tried to set these bits to zero
  40. * (UART doesn't work after the 'reset run' command).
  41. */
  42. #define CONFIG_SYS_HRCW_HIGH (\
  43. HRCWH_PCI_HOST |\
  44. HRCWH_PCI1_ARBITER_ENABLE |\
  45. HRCWH_CORE_ENABLE |\
  46. HRCWH_FROM_0XFFF00100 |\
  47. HRCWH_BOOTSEQ_DISABLE |\
  48. HRCWH_SW_WATCHDOG_DISABLE |\
  49. HRCWH_ROM_LOC_LOCAL_16BIT |\
  50. HRCWH_RL_EXT_LEGACY |\
  51. HRCWH_TSEC1M_IN_MII |\
  52. HRCWH_TSEC2M_IN_RGMII |\
  53. HRCWH_BIG_ENDIAN)
  54. /*
  55. * System IO Config
  56. */
  57. #define CONFIG_SYS_SICRH (\
  58. SICRH_ESDHC_A_SD |\
  59. SICRH_ESDHC_B_SD |\
  60. SICRH_ESDHC_C_SD |\
  61. SICRH_GPIO_A_GPIO |\
  62. SICRH_GPIO_B_GPIO |\
  63. SICRH_IEEE1588_A_GPIO |\
  64. SICRH_USB |\
  65. SICRH_GTM_GPIO |\
  66. SICRH_IEEE1588_B_GPIO |\
  67. SICRH_ETSEC2_GPIO |\
  68. SICRH_GPIOSEL_1 |\
  69. SICRH_TMROBI_V3P3 |\
  70. SICRH_TSOBI1_V2P5 |\
  71. SICRH_TSOBI2_V2P5) /* 0x0037f103 */
  72. #define CONFIG_SYS_SICRL (\
  73. SICRL_SPI_PF0 |\
  74. SICRL_UART_PF0 |\
  75. SICRL_IRQ_PF0 |\
  76. SICRL_I2C2_PF0 |\
  77. SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
  78. /*
  79. * IMMR new address
  80. */
  81. #define CONFIG_SYS_IMMR 0xE0000000
  82. /*
  83. * SERDES
  84. */
  85. #define CONFIG_FSL_SERDES
  86. #define CONFIG_FSL_SERDES1 0xe3000
  87. /*
  88. * Arbiter Setup
  89. */
  90. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  91. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
  92. #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
  93. /*
  94. * DDR Setup
  95. */
  96. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
  97. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  98. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  99. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  100. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  101. | DDRCDR_PZ_LOZ \
  102. | DDRCDR_NZ_LOZ \
  103. | DDRCDR_ODT \
  104. | DDRCDR_Q_DRN)
  105. /* 0x7b880001 */
  106. /*
  107. * Manually set up DDR parameters
  108. * consist of one chip NT5TU64M16HG from NANYA
  109. */
  110. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  111. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  112. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  113. | CSCONFIG_ODT_RD_NEVER \
  114. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  115. | CSCONFIG_BANK_BIT_3 \
  116. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  117. /* 0x80010102 */
  118. #define CONFIG_SYS_DDR_TIMING_3 0
  119. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  120. | (0 << TIMING_CFG0_WRT_SHIFT) \
  121. | (0 << TIMING_CFG0_RRT_SHIFT) \
  122. | (0 << TIMING_CFG0_WWT_SHIFT) \
  123. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  124. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  125. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  126. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  127. /* 0x00260802 */
  128. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  129. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  130. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  131. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  132. | (9 << TIMING_CFG1_REFREC_SHIFT) \
  133. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  134. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  135. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  136. /* 0x26279222 */
  137. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  138. | (4 << TIMING_CFG2_CPO_SHIFT) \
  139. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  140. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  141. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  142. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  143. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  144. /* 0x021848c5 */
  145. #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  146. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  147. /* 0x08240100 */
  148. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  149. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  150. | SDRAM_CFG_DBW_16)
  151. /* 0x43100000 */
  152. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  153. #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  154. | (0x0242 << SDRAM_MODE_SD_SHIFT))
  155. /* ODT 150ohm CL=4, AL=0 on SDRAM */
  156. #define CONFIG_SYS_DDR_MODE2 0x00000000
  157. /*
  158. * Memory test
  159. */
  160. #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
  161. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  162. /*
  163. * The reserved memory
  164. */
  165. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  166. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  167. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  168. /*
  169. * Initial RAM Base Address Setup
  170. */
  171. #define CONFIG_SYS_INIT_RAM_LOCK 1
  172. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  173. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  174. #define CONFIG_SYS_GBL_DATA_OFFSET \
  175. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  176. /*
  177. * Local Bus Configuration & Clock Setup
  178. */
  179. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  180. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  181. #define CONFIG_SYS_LBC_LBCR 0x00040000
  182. /*
  183. * FLASH on the Local Bus
  184. */
  185. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  186. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  187. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  188. #define CONFIG_FLASH_CFI_LEGACY
  189. #define CONFIG_SYS_FLASH_LEGACY_512Kx16
  190. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  191. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
  192. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  193. /* Window base at flash base */
  194. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  195. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  196. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  197. | BR_PS_16 /* 16 bit port */ \
  198. | BR_MS_GPCM /* MSEL = GPCM */ \
  199. | BR_V) /* valid */
  200. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  201. | OR_UPM_XAM \
  202. | OR_GPCM_CSNT \
  203. | OR_GPCM_ACS_DIV2 \
  204. | OR_GPCM_XACS \
  205. | OR_GPCM_SCY_15 \
  206. | OR_GPCM_TRLX_SET \
  207. | OR_GPCM_EHTR_SET)
  208. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  209. #define CONFIG_SYS_MAX_FLASH_SECT 135
  210. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  211. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  212. /*
  213. * FPGA
  214. */
  215. #define CONFIG_SYS_FPGA0_BASE 0xE0600000
  216. #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
  217. /* Window base at FPGA base */
  218. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
  219. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
  220. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
  221. | BR_PS_16 /* 16 bit port */ \
  222. | BR_MS_GPCM /* MSEL = GPCM */ \
  223. | BR_V) /* valid */
  224. #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
  225. | OR_UPM_XAM \
  226. | OR_GPCM_CSNT \
  227. | OR_GPCM_SCY_5 \
  228. | OR_GPCM_TRLX_CLEAR \
  229. | OR_GPCM_EHTR_CLEAR)
  230. #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
  231. #define CONFIG_SYS_FPGA_DONE(k) 0x0010
  232. #define CONFIG_SYS_FPGA_COUNT 1
  233. #define CONFIG_SYS_MCLINK_MAX 3
  234. #define CONFIG_SYS_FPGA_PTR \
  235. { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
  236. #define CONFIG_SYS_FPGA_NO_RFL_HI
  237. /*
  238. * Serial Port
  239. */
  240. #define CONFIG_SYS_NS16550_SERIAL
  241. #define CONFIG_SYS_NS16550_REG_SIZE 1
  242. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  243. #define CONFIG_SYS_BAUDRATE_TABLE \
  244. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  245. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  246. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  247. /* Pass open firmware flat tree */
  248. /* I2C */
  249. #define CONFIG_SYS_I2C
  250. #define CONFIG_SYS_I2C_FSL
  251. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  252. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  253. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  254. #define CONFIG_PCA953X /* NXP PCA9554 */
  255. #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
  256. {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
  257. #define CONFIG_PCA9698 /* NXP PCA9698 */
  258. #define CONFIG_SYS_I2C_IHS
  259. #define CONFIG_SYS_I2C_IHS_CH0
  260. #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
  261. #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
  262. #define CONFIG_SYS_I2C_IHS_CH1
  263. #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
  264. #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
  265. #define CONFIG_SYS_I2C_IHS_CH2
  266. #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
  267. #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
  268. #define CONFIG_SYS_I2C_IHS_CH3
  269. #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
  270. #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
  271. #ifdef CONFIG_STRIDER_CON_DP
  272. #define CONFIG_SYS_I2C_IHS_DUAL
  273. #define CONFIG_SYS_I2C_IHS_CH0_1
  274. #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
  275. #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
  276. #define CONFIG_SYS_I2C_IHS_CH1_1
  277. #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
  278. #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
  279. #define CONFIG_SYS_I2C_IHS_CH2_1
  280. #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
  281. #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
  282. #define CONFIG_SYS_I2C_IHS_CH3_1
  283. #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
  284. #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
  285. #endif
  286. /*
  287. * Software (bit-bang) I2C driver configuration
  288. */
  289. #define CONFIG_SYS_I2C_SOFT
  290. #define CONFIG_SOFT_I2C_READ_REPEATED_START
  291. #define CONFIG_SYS_I2C_SOFT_SPEED 50000
  292. #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
  293. #define I2C_SOFT_DECLARATIONS2
  294. #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
  295. #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
  296. #define I2C_SOFT_DECLARATIONS3
  297. #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
  298. #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
  299. #define I2C_SOFT_DECLARATIONS4
  300. #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
  301. #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
  302. #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
  303. #define I2C_SOFT_DECLARATIONS5
  304. #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
  305. #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
  306. #define I2C_SOFT_DECLARATIONS6
  307. #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
  308. #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
  309. #define I2C_SOFT_DECLARATIONS7
  310. #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
  311. #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
  312. #define I2C_SOFT_DECLARATIONS8
  313. #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
  314. #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
  315. #endif
  316. #ifdef CONFIG_STRIDER_CON_DP
  317. #define I2C_SOFT_DECLARATIONS9
  318. #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
  319. #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
  320. #define I2C_SOFT_DECLARATIONS10
  321. #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
  322. #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
  323. #define I2C_SOFT_DECLARATIONS11
  324. #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
  325. #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
  326. #define I2C_SOFT_DECLARATIONS12
  327. #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
  328. #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
  329. #endif
  330. #ifdef CONFIG_STRIDER_CON
  331. #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
  332. #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
  333. #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
  334. #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  335. #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
  336. {12, 0x4c} }
  337. #elif defined(CONFIG_STRIDER_CON_DP)
  338. #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
  339. #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
  340. #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
  341. #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
  342. #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
  343. {12, 0x4c} }
  344. #elif defined(CONFIG_STRIDER_CPU_DP)
  345. #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
  346. #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
  347. #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  348. #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
  349. {8, 0x4c} }
  350. #else
  351. #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
  352. #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
  353. #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  354. #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
  355. {4, 0x18} }
  356. #endif
  357. #ifndef __ASSEMBLY__
  358. void fpga_gpio_set(unsigned int bus, int pin);
  359. void fpga_gpio_clear(unsigned int bus, int pin);
  360. int fpga_gpio_get(unsigned int bus, int pin);
  361. void fpga_control_set(unsigned int bus, int pin);
  362. void fpga_control_clear(unsigned int bus, int pin);
  363. #endif
  364. #ifdef CONFIG_STRIDER_CON
  365. #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
  366. #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
  367. #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
  368. (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
  369. #elif defined(CONFIG_STRIDER_CON_DP)
  370. #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
  371. #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
  372. #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
  373. #else
  374. #define I2C_SDA_GPIO 0x0040
  375. #define I2C_SCL_GPIO 0x0020
  376. #define I2C_FPGA_IDX I2C_ADAP_HWNR
  377. #endif
  378. #ifdef CONFIG_STRIDER_CON_DP
  379. #define I2C_ACTIVE \
  380. do { \
  381. if (I2C_ADAP_HWNR > 7) \
  382. fpga_control_set(I2C_FPGA_IDX, 0x0004); \
  383. else \
  384. fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
  385. } while (0)
  386. #else
  387. #define I2C_ACTIVE { }
  388. #endif
  389. #define I2C_TRISTATE { }
  390. #define I2C_READ \
  391. (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
  392. #define I2C_SDA(bit) \
  393. do { \
  394. if (bit) \
  395. fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  396. else \
  397. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  398. } while (0)
  399. #define I2C_SCL(bit) \
  400. do { \
  401. if (bit) \
  402. fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  403. else \
  404. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  405. } while (0)
  406. #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
  407. /*
  408. * Software (bit-bang) MII driver configuration
  409. */
  410. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  411. #define CONFIG_BITBANGMII_MULTI
  412. /*
  413. * OSD Setup
  414. */
  415. #define CONFIG_SYS_OSD_SCREENS 1
  416. #define CONFIG_SYS_DP501_DIFFERENTIAL
  417. #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
  418. #ifdef CONFIG_STRIDER_CON_DP
  419. #define CONFIG_SYS_OSD_DH
  420. #endif
  421. /*
  422. * General PCI
  423. * Addresses are mapped 1-1.
  424. */
  425. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  426. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  427. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  428. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  429. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  430. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  431. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  432. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  433. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  434. /* enable PCIE clock */
  435. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  436. #define CONFIG_PCI_INDIRECT_BRIDGE
  437. #define CONFIG_PCIE
  438. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  439. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  440. /*
  441. * TSEC
  442. */
  443. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  444. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  445. /*
  446. * TSEC ethernet configuration
  447. */
  448. #define CONFIG_MII 1 /* MII PHY management */
  449. #define CONFIG_TSEC1
  450. #define CONFIG_TSEC1_NAME "eTSEC0"
  451. #define TSEC1_PHY_ADDR 1
  452. #define TSEC1_PHYIDX 0
  453. #define TSEC1_FLAGS 0
  454. /* Options are: eTSEC[0-1] */
  455. #define CONFIG_ETHPRIME "eTSEC0"
  456. /*
  457. * Environment
  458. */
  459. #if 1
  460. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  461. CONFIG_SYS_MONITOR_LEN)
  462. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  463. #define CONFIG_ENV_SIZE 0x2000
  464. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  465. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  466. #else
  467. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  468. #endif
  469. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  470. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  471. /*
  472. * Command line configuration.
  473. */
  474. /*
  475. * Miscellaneous configurable options
  476. */
  477. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  478. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  479. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  480. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  481. /*
  482. * For booting Linux, the board info and command line data
  483. * have to be in the first 256 MB of memory, since this is
  484. * the maximum mapped by the Linux kernel during initialization.
  485. */
  486. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  487. /*
  488. * Core HID Setup
  489. */
  490. #define CONFIG_SYS_HID0_INIT 0x000000000
  491. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  492. HID0_ENABLE_INSTRUCTION_CACHE | \
  493. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  494. #define CONFIG_SYS_HID2 HID2_HBE
  495. /*
  496. * MMU Setup
  497. */
  498. /* DDR: cache cacheable */
  499. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
  500. BATL_MEMCOHERENCE)
  501. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
  502. BATU_VS | BATU_VP)
  503. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  504. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  505. /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
  506. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
  507. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  508. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
  509. BATU_VP)
  510. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  511. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  512. /* FLASH: icache cacheable, but dcache-inhibit and guarded */
  513. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  514. BATL_MEMCOHERENCE)
  515. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
  516. BATU_VS | BATU_VP)
  517. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  518. BATL_CACHEINHIBIT | \
  519. BATL_GUARDEDSTORAGE)
  520. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  521. /* Stack in dcache: cacheable, no memory coherence */
  522. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
  523. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
  524. BATU_VS | BATU_VP)
  525. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  526. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  527. /*
  528. * Environment Configuration
  529. */
  530. #define CONFIG_ENV_OVERWRITE
  531. #if defined(CONFIG_TSEC_ENET)
  532. #define CONFIG_HAS_ETH0
  533. #endif
  534. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  535. #define CONFIG_HOSTNAME "hrcon"
  536. #define CONFIG_ROOTPATH "/opt/nfsroot"
  537. #define CONFIG_BOOTFILE "uImage"
  538. #define CONFIG_PREBOOT /* enable preboot variable */
  539. #define CONFIG_EXTRA_ENV_SETTINGS \
  540. "netdev=eth0\0" \
  541. "consoledev=ttyS1\0" \
  542. "u-boot=u-boot.bin\0" \
  543. "kernel_addr=1000000\0" \
  544. "fdt_addr=C00000\0" \
  545. "fdtfile=hrcon.dtb\0" \
  546. "load=tftp ${loadaddr} ${u-boot}\0" \
  547. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  548. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  549. " +${filesize};cp.b ${fileaddr} " \
  550. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  551. "upd=run load update\0" \
  552. #define CONFIG_NFSBOOTCOMMAND \
  553. "setenv bootargs root=/dev/nfs rw " \
  554. "nfsroot=$serverip:$rootpath " \
  555. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  556. "console=$consoledev,$baudrate $othbootargs;" \
  557. "tftp ${kernel_addr} $bootfile;" \
  558. "tftp ${fdt_addr} $fdtfile;" \
  559. "bootm ${kernel_addr} - ${fdt_addr}"
  560. #define CONFIG_MMCBOOTCOMMAND \
  561. "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
  562. "console=$consoledev,$baudrate $othbootargs;" \
  563. "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
  564. "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
  565. "bootm ${kernel_addr} - ${fdt_addr}"
  566. #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
  567. #endif /* __CONFIG_H */