sbc8349.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WindRiver SBC8349 U-Boot configuration file.
  4. * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on the MPC8349EMDS config.
  8. */
  9. /*
  10. * sbc8349 board configuration file.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1 /* E300 Family */
  18. #define CONFIG_MPC834x 1 /* MPC834x family */
  19. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  20. /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  21. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  22. /*
  23. * The default if PCI isn't enabled, or if no PCI clk setting is given
  24. * is 66MHz; this is what the board defaults to when the PCI slot is
  25. * physically empty. The board will automatically (i.e w/o jumpers)
  26. * clock down to 33MHz if you insert a 33MHz PCI card.
  27. */
  28. #ifdef CONFIG_PCI_33M
  29. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  30. #else /* 66M */
  31. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  32. #endif
  33. #ifndef CONFIG_SYS_CLK_FREQ
  34. #ifdef CONFIG_PCI_33M
  35. #define CONFIG_SYS_CLK_FREQ 33000000
  36. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  37. #else /* 66M */
  38. #define CONFIG_SYS_CLK_FREQ 66000000
  39. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  40. #endif
  41. #endif
  42. #define CONFIG_SYS_IMMR 0xE0000000
  43. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  44. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  45. #define CONFIG_SYS_MEMTEST_END 0x00100000
  46. /*
  47. * DDR Setup
  48. */
  49. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  50. #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  51. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  52. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
  53. /*
  54. * 32-bit data path mode.
  55. *
  56. * Please note that using this mode for devices with the real density of 64-bit
  57. * effectively reduces the amount of available memory due to the effect of
  58. * wrapping around while translating address to row/columns, for example in the
  59. * 256MB module the upper 128MB get aliased with contents of the lower
  60. * 128MB); normally this define should be used for devices with real 32-bit
  61. * data path.
  62. */
  63. #undef CONFIG_DDR_32BIT
  64. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  65. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  66. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  67. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
  68. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  69. #define CONFIG_DDR_2T_TIMING
  70. #if defined(CONFIG_SPD_EEPROM)
  71. /*
  72. * Determine DDR configuration from I2C interface.
  73. */
  74. #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
  75. #else
  76. /*
  77. * Manually set up DDR parameters
  78. * NB: manual DDR setup untested on sbc834x
  79. */
  80. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  81. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  82. | CSCONFIG_ROW_BIT_13 \
  83. | CSCONFIG_COL_BIT_10)
  84. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  85. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  86. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  87. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  88. #if defined(CONFIG_DDR_32BIT)
  89. /* set burst length to 8 for 32-bit data path */
  90. /* DLL,normal,seq,4/2.5, 8 burst len */
  91. #define CONFIG_SYS_DDR_MODE 0x00000023
  92. #else
  93. /* the default burst length is 4 - for 64-bit data path */
  94. /* DLL,normal,seq,4/2.5, 4 burst len */
  95. #define CONFIG_SYS_DDR_MODE 0x00000022
  96. #endif
  97. #endif
  98. /*
  99. * SDRAM on the Local Bus
  100. */
  101. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  102. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  103. /*
  104. * FLASH on the Local Bus
  105. */
  106. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  107. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  108. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  109. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  110. /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
  111. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  112. | BR_PS_16 /* 16 bit port */ \
  113. | BR_MS_GPCM /* MSEL = GPCM */ \
  114. | BR_V) /* valid */
  115. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  116. | OR_GPCM_XAM \
  117. | OR_GPCM_CSNT \
  118. | OR_GPCM_ACS_DIV2 \
  119. | OR_GPCM_XACS \
  120. | OR_GPCM_SCY_15 \
  121. | OR_GPCM_TRLX_SET \
  122. | OR_GPCM_EHTR_SET \
  123. | OR_GPCM_EAD)
  124. /* 0xFF806FF7 */
  125. /* window base at flash base */
  126. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  127. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  128. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  129. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  130. #undef CONFIG_SYS_FLASH_CHECKSUM
  131. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  132. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  133. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  134. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  135. #define CONFIG_SYS_RAMBOOT
  136. #else
  137. #undef CONFIG_SYS_RAMBOOT
  138. #endif
  139. #define CONFIG_SYS_INIT_RAM_LOCK 1
  140. /* Initial RAM address */
  141. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  142. /* Size of used area in RAM*/
  143. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  144. #define CONFIG_SYS_GBL_DATA_OFFSET \
  145. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  146. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  147. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  148. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  149. /*
  150. * Local Bus LCRR and LBCR regs
  151. * LCRR: DLL bypass, Clock divider is 4
  152. * External Local Bus rate is
  153. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  154. */
  155. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  156. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  157. #define CONFIG_SYS_LBC_LBCR 0x00000000
  158. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  159. #ifdef CONFIG_SYS_LB_SDRAM
  160. /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
  161. /*
  162. * Base Register 2 and Option Register 2 configure SDRAM.
  163. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  164. *
  165. * For BR2, need:
  166. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  167. * port-size = 32-bits = BR2[19:20] = 11
  168. * no parity checking = BR2[21:22] = 00
  169. * SDRAM for MSEL = BR2[24:26] = 011
  170. * Valid = BR[31] = 1
  171. *
  172. * 0 4 8 12 16 20 24 28
  173. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  174. */
  175. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  176. | BR_PS_32 \
  177. | BR_MS_SDRAM \
  178. | BR_V)
  179. /* 0xF0001861 */
  180. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  181. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  182. /*
  183. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  184. *
  185. * For OR2, need:
  186. * 64MB mask for AM, OR2[0:7] = 1111 1100
  187. * XAM, OR2[17:18] = 11
  188. * 9 columns OR2[19-21] = 010
  189. * 13 rows OR2[23-25] = 100
  190. * EAD set for extra time OR[31] = 1
  191. *
  192. * 0 4 8 12 16 20 24 28
  193. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  194. */
  195. #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
  196. | OR_SDRAM_XAM \
  197. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  198. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  199. | OR_SDRAM_EAD)
  200. /* 0xFC006901 */
  201. /* LB sdram refresh timer, about 6us */
  202. #define CONFIG_SYS_LBC_LSRT 0x32000000
  203. /* LB refresh timer prescal, 266MHz/32 */
  204. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  205. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  206. | LSDMR_BSMA1516 \
  207. | LSDMR_RFCR8 \
  208. | LSDMR_PRETOACT6 \
  209. | LSDMR_ACTTORW3 \
  210. | LSDMR_BL8 \
  211. | LSDMR_WRC3 \
  212. | LSDMR_CL3)
  213. /*
  214. * SDRAM Controller configuration sequence.
  215. */
  216. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  217. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  218. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  219. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  220. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  221. #endif
  222. /*
  223. * Serial Port
  224. */
  225. #define CONFIG_SYS_NS16550_SERIAL
  226. #define CONFIG_SYS_NS16550_REG_SIZE 1
  227. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  228. #define CONFIG_SYS_BAUDRATE_TABLE \
  229. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  230. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  231. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  232. /* I2C */
  233. #define CONFIG_SYS_I2C
  234. #define CONFIG_SYS_I2C_FSL
  235. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  236. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  237. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  238. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  239. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  240. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  241. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
  242. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  243. /* TSEC */
  244. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  245. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  246. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  247. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  248. /*
  249. * General PCI
  250. * Addresses are mapped 1-1.
  251. */
  252. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  253. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  254. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  255. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  256. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  257. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  258. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  259. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  260. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  261. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  262. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  263. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  264. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  265. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  266. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  267. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  268. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  269. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  270. #if defined(CONFIG_PCI)
  271. #define PCI_64BIT
  272. #define PCI_ONE_PCI1
  273. #if defined(PCI_64BIT)
  274. #undef PCI_ALL_PCI1
  275. #undef PCI_TWO_PCI1
  276. #undef PCI_ONE_PCI1
  277. #endif
  278. #undef CONFIG_EEPRO100
  279. #undef CONFIG_TULIP
  280. #if !defined(CONFIG_PCI_PNP)
  281. #define PCI_ENET0_IOADDR 0xFIXME
  282. #define PCI_ENET0_MEMADDR 0xFIXME
  283. #define PCI_IDSEL_NUMBER 0xFIXME
  284. #endif
  285. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  286. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  287. #endif /* CONFIG_PCI */
  288. /*
  289. * TSEC configuration
  290. */
  291. #if defined(CONFIG_TSEC_ENET)
  292. #define CONFIG_TSEC1 1
  293. #define CONFIG_TSEC1_NAME "TSEC0"
  294. #define CONFIG_TSEC2 1
  295. #define CONFIG_TSEC2_NAME "TSEC1"
  296. #define CONFIG_PHY_BCM5421S 1
  297. #define TSEC1_PHY_ADDR 0x19
  298. #define TSEC2_PHY_ADDR 0x1a
  299. #define TSEC1_PHYIDX 0
  300. #define TSEC2_PHYIDX 0
  301. #define TSEC1_FLAGS TSEC_GIGABIT
  302. #define TSEC2_FLAGS TSEC_GIGABIT
  303. /* Options are: TSEC[0-1] */
  304. #define CONFIG_ETHPRIME "TSEC0"
  305. #endif /* CONFIG_TSEC_ENET */
  306. /*
  307. * Environment
  308. */
  309. #ifndef CONFIG_SYS_RAMBOOT
  310. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  311. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  312. #define CONFIG_ENV_SIZE 0x2000
  313. /* Address and size of Redundant Environment Sector */
  314. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  315. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  316. #else
  317. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  318. #define CONFIG_ENV_SIZE 0x2000
  319. #endif
  320. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  321. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  322. /*
  323. * BOOTP options
  324. */
  325. #define CONFIG_BOOTP_BOOTFILESIZE
  326. /*
  327. * Command line configuration.
  328. */
  329. #undef CONFIG_WATCHDOG /* watchdog disabled */
  330. /*
  331. * Miscellaneous configurable options
  332. */
  333. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  334. /*
  335. * For booting Linux, the board info and command line data
  336. * have to be in the first 256 MB of memory, since this is
  337. * the maximum mapped by the Linux kernel during initialization.
  338. */
  339. /* Initial Memory map for Linux*/
  340. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  341. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  342. #if 1 /*528/264*/
  343. #define CONFIG_SYS_HRCW_LOW (\
  344. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  345. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  346. HRCWL_CSB_TO_CLKIN |\
  347. HRCWL_VCO_1X2 |\
  348. HRCWL_CORE_TO_CSB_2X1)
  349. #elif 0 /*396/132*/
  350. #define CONFIG_SYS_HRCW_LOW (\
  351. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  352. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  353. HRCWL_CSB_TO_CLKIN |\
  354. HRCWL_VCO_1X4 |\
  355. HRCWL_CORE_TO_CSB_3X1)
  356. #elif 0 /*264/132*/
  357. #define CONFIG_SYS_HRCW_LOW (\
  358. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  359. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  360. HRCWL_CSB_TO_CLKIN |\
  361. HRCWL_VCO_1X4 |\
  362. HRCWL_CORE_TO_CSB_2X1)
  363. #elif 0 /*132/132*/
  364. #define CONFIG_SYS_HRCW_LOW (\
  365. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  366. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  367. HRCWL_CSB_TO_CLKIN |\
  368. HRCWL_VCO_1X4 |\
  369. HRCWL_CORE_TO_CSB_1X1)
  370. #elif 0 /*264/264 */
  371. #define CONFIG_SYS_HRCW_LOW (\
  372. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  373. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  374. HRCWL_CSB_TO_CLKIN |\
  375. HRCWL_VCO_1X4 |\
  376. HRCWL_CORE_TO_CSB_1X1)
  377. #endif
  378. #if defined(PCI_64BIT)
  379. #define CONFIG_SYS_HRCW_HIGH (\
  380. HRCWH_PCI_HOST |\
  381. HRCWH_64_BIT_PCI |\
  382. HRCWH_PCI1_ARBITER_ENABLE |\
  383. HRCWH_PCI2_ARBITER_DISABLE |\
  384. HRCWH_CORE_ENABLE |\
  385. HRCWH_FROM_0X00000100 |\
  386. HRCWH_BOOTSEQ_DISABLE |\
  387. HRCWH_SW_WATCHDOG_DISABLE |\
  388. HRCWH_ROM_LOC_LOCAL_16BIT |\
  389. HRCWH_TSEC1M_IN_GMII |\
  390. HRCWH_TSEC2M_IN_GMII)
  391. #else
  392. #define CONFIG_SYS_HRCW_HIGH (\
  393. HRCWH_PCI_HOST |\
  394. HRCWH_32_BIT_PCI |\
  395. HRCWH_PCI1_ARBITER_ENABLE |\
  396. HRCWH_PCI2_ARBITER_ENABLE |\
  397. HRCWH_CORE_ENABLE |\
  398. HRCWH_FROM_0X00000100 |\
  399. HRCWH_BOOTSEQ_DISABLE |\
  400. HRCWH_SW_WATCHDOG_DISABLE |\
  401. HRCWH_ROM_LOC_LOCAL_16BIT |\
  402. HRCWH_TSEC1M_IN_GMII |\
  403. HRCWH_TSEC2M_IN_GMII)
  404. #endif
  405. /* System IO Config */
  406. #define CONFIG_SYS_SICRH 0
  407. #define CONFIG_SYS_SICRL SICRL_LDP_A
  408. #define CONFIG_SYS_HID0_INIT 0x000000000
  409. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  410. | HID0_ENABLE_INSTRUCTION_CACHE)
  411. /* #define CONFIG_SYS_HID0_FINAL (\
  412. HID0_ENABLE_INSTRUCTION_CACHE |\
  413. HID0_ENABLE_M_BIT |\
  414. HID0_ENABLE_ADDRESS_BROADCAST) */
  415. #define CONFIG_SYS_HID2 HID2_HBE
  416. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  417. /* DDR @ 0x00000000 */
  418. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  419. | BATL_PP_RW \
  420. | BATL_MEMCOHERENCE)
  421. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  422. | BATU_BL_256M \
  423. | BATU_VS \
  424. | BATU_VP)
  425. /* PCI @ 0x80000000 */
  426. #ifdef CONFIG_PCI
  427. #define CONFIG_PCI_INDIRECT_BRIDGE
  428. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  429. | BATL_PP_RW \
  430. | BATL_MEMCOHERENCE)
  431. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  432. | BATU_BL_256M \
  433. | BATU_VS \
  434. | BATU_VP)
  435. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  436. | BATL_PP_RW \
  437. | BATL_CACHEINHIBIT \
  438. | BATL_GUARDEDSTORAGE)
  439. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  440. | BATU_BL_256M \
  441. | BATU_VS \
  442. | BATU_VP)
  443. #else
  444. #define CONFIG_SYS_IBAT1L (0)
  445. #define CONFIG_SYS_IBAT1U (0)
  446. #define CONFIG_SYS_IBAT2L (0)
  447. #define CONFIG_SYS_IBAT2U (0)
  448. #endif
  449. #ifdef CONFIG_MPC83XX_PCI2
  450. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  451. | BATL_PP_RW \
  452. | BATL_MEMCOHERENCE)
  453. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  454. | BATU_BL_256M \
  455. | BATU_VS \
  456. | BATU_VP)
  457. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  458. | BATL_PP_RW \
  459. | BATL_CACHEINHIBIT \
  460. | BATL_GUARDEDSTORAGE)
  461. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  462. | BATU_BL_256M \
  463. | BATU_VS \
  464. | BATU_VP)
  465. #else
  466. #define CONFIG_SYS_IBAT3L (0)
  467. #define CONFIG_SYS_IBAT3U (0)
  468. #define CONFIG_SYS_IBAT4L (0)
  469. #define CONFIG_SYS_IBAT4U (0)
  470. #endif
  471. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
  472. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  473. | BATL_PP_RW \
  474. | BATL_CACHEINHIBIT \
  475. | BATL_GUARDEDSTORAGE)
  476. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  477. | BATU_BL_256M \
  478. | BATU_VS \
  479. | BATU_VP)
  480. /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  481. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
  482. | BATL_PP_RW \
  483. | BATL_MEMCOHERENCE \
  484. | BATL_GUARDEDSTORAGE)
  485. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
  486. | BATU_BL_256M \
  487. | BATU_VS \
  488. | BATU_VP)
  489. #define CONFIG_SYS_IBAT7L (0)
  490. #define CONFIG_SYS_IBAT7U (0)
  491. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  492. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  493. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  494. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  495. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  496. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  497. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  498. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  499. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  500. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  501. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  502. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  503. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  504. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  505. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  506. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  507. #if defined(CONFIG_CMD_KGDB)
  508. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  509. #endif
  510. /*
  511. * Environment Configuration
  512. */
  513. #define CONFIG_ENV_OVERWRITE
  514. #if defined(CONFIG_TSEC_ENET)
  515. #define CONFIG_HAS_ETH0
  516. #define CONFIG_HAS_ETH1
  517. #endif
  518. #define CONFIG_HOSTNAME "SBC8349"
  519. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  520. #define CONFIG_BOOTFILE "uImage"
  521. /* default location for tftp and bootm */
  522. #define CONFIG_LOADADDR 800000
  523. #define CONFIG_EXTRA_ENV_SETTINGS \
  524. "netdev=eth0\0" \
  525. "hostname=sbc8349\0" \
  526. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  527. "nfsroot=${serverip}:${rootpath}\0" \
  528. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  529. "addip=setenv bootargs ${bootargs} " \
  530. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  531. ":${hostname}:${netdev}:off panic=1\0" \
  532. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  533. "flash_nfs=run nfsargs addip addtty;" \
  534. "bootm ${kernel_addr}\0" \
  535. "flash_self=run ramargs addip addtty;" \
  536. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  537. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  538. "bootm\0" \
  539. "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
  540. "update=protect off ff800000 ff83ffff; " \
  541. "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
  542. "upd=run load update\0" \
  543. "fdtaddr=780000\0" \
  544. "fdtfile=sbc8349.dtb\0" \
  545. ""
  546. #define CONFIG_NFSBOOTCOMMAND \
  547. "setenv bootargs root=/dev/nfs rw " \
  548. "nfsroot=$serverip:$rootpath " \
  549. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  550. "$netdev:off " \
  551. "console=$consoledev,$baudrate $othbootargs;" \
  552. "tftp $loadaddr $bootfile;" \
  553. "tftp $fdtaddr $fdtfile;" \
  554. "bootm $loadaddr - $fdtaddr"
  555. #define CONFIG_RAMBOOTCOMMAND \
  556. "setenv bootargs root=/dev/ram rw " \
  557. "console=$consoledev,$baudrate $othbootargs;" \
  558. "tftp $ramdiskaddr $ramdiskfile;" \
  559. "tftp $loadaddr $bootfile;" \
  560. "tftp $fdtaddr $fdtfile;" \
  561. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  562. #define CONFIG_BOOTCOMMAND "run flash_self"
  563. #endif /* __CONFIG_H */