sama5d3_xplained.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the SAMA5D3 Xplained board.
  4. *
  5. * Copyright (C) 2014 Atmel Corporation
  6. * Bo Shen <voice.shen@atmel.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include "at91-sama5_common.h"
  11. /*
  12. * This needs to be defined for the OHCI code to work but it is defined as
  13. * ATMEL_ID_UHPHS in the CPU specific header files.
  14. */
  15. #define ATMEL_ID_UHP 32
  16. /*
  17. * Specify the clock enable bit in the PMC_SCER register.
  18. */
  19. #define ATMEL_PMC_UHP (1 << 6)
  20. /* SDRAM */
  21. #define CONFIG_NR_DRAM_BANKS 1
  22. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  23. #define CONFIG_SYS_SDRAM_SIZE 0x10000000
  24. #ifdef CONFIG_SPL_BUILD
  25. #define CONFIG_SYS_INIT_SP_ADDR 0x318000
  26. #else
  27. #define CONFIG_SYS_INIT_SP_ADDR \
  28. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  29. #endif
  30. /* NAND flash */
  31. #ifdef CONFIG_CMD_NAND
  32. #define CONFIG_NAND_ATMEL
  33. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  34. #define CONFIG_SYS_NAND_BASE 0x60000000
  35. /* our ALE is AD21 */
  36. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  37. /* our CLE is AD22 */
  38. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  39. #define CONFIG_SYS_NAND_ONFI_DETECTION
  40. #define CONFIG_MTD_DEVICE
  41. #define CONFIG_MTD_PARTITIONS
  42. #endif
  43. /* PMECC & PMERRLOC */
  44. #define CONFIG_ATMEL_NAND_HWECC
  45. #define CONFIG_ATMEL_NAND_HW_PMECC
  46. #define CONFIG_PMECC_CAP 4
  47. #define CONFIG_PMECC_SECTOR_SIZE 512
  48. /* USB */
  49. #ifdef CONFIG_CMD_USB
  50. #define CONFIG_USB_ATMEL
  51. #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  52. #define CONFIG_USB_OHCI_NEW
  53. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  54. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
  55. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
  56. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  57. #endif
  58. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  59. /* SPL */
  60. #define CONFIG_SPL_TEXT_BASE 0x300000
  61. #define CONFIG_SPL_MAX_SIZE 0x18000
  62. #define CONFIG_SPL_BSS_START_ADDR 0x20000000
  63. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  64. #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  65. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  66. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  67. #ifdef CONFIG_SD_BOOT
  68. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  69. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  70. #elif CONFIG_NAND_BOOT
  71. #define CONFIG_SPL_NAND_DRIVERS
  72. #define CONFIG_SPL_NAND_BASE
  73. #endif
  74. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  75. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  76. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  77. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  78. #define CONFIG_SYS_NAND_OOBSIZE 64
  79. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  80. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  81. #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
  82. #endif