r2dplus.h 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586
  1. #ifndef __CONFIG_H
  2. #define __CONFIG_H
  3. #define CONFIG_CPU_SH7751 1
  4. #define __LITTLE_ENDIAN__ 1
  5. #define CONFIG_DISPLAY_BOARDINFO
  6. /* SCIF */
  7. #define CONFIG_CONS_SCIF1 1
  8. #define CONFIG_ENV_OVERWRITE 1
  9. /* SDRAM */
  10. #define CONFIG_SYS_SDRAM_BASE 0x8C000000
  11. #define CONFIG_SYS_SDRAM_SIZE 0x04000000
  12. #define CONFIG_SYS_PBSIZE 256
  13. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
  14. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
  15. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  16. /* Address of u-boot image in Flash */
  17. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
  18. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  19. /* Size of DRAM reserved for malloc() use */
  20. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  21. #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  22. /*
  23. * NOR Flash ( Spantion S29GL256P )
  24. */
  25. #define CONFIG_SYS_FLASH_CFI
  26. #define CONFIG_FLASH_CFI_DRIVER
  27. #define CONFIG_SYS_FLASH_BASE (0xA0000000)
  28. #define CONFIG_SYS_MAX_FLASH_BANKS (1)
  29. #define CONFIG_SYS_MAX_FLASH_SECT 256
  30. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  31. #define CONFIG_ENV_SECT_SIZE 0x40000
  32. #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  33. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  34. /*
  35. * SuperH Clock setting
  36. */
  37. #define CONFIG_SYS_CLK_FREQ 60000000
  38. #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  39. #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  40. #define CONFIG_SYS_TMU_CLK_DIV 4
  41. #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
  42. /*
  43. * IDE support
  44. */
  45. #define CONFIG_IDE_RESET 1
  46. #define CONFIG_SYS_PIO_MODE 1
  47. #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
  48. #define CONFIG_SYS_IDE_MAXDEVICE 1
  49. #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
  50. #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
  51. #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
  52. #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
  53. #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
  54. #define CONFIG_IDE_SWAP_IO
  55. /*
  56. * SuperH PCI Bridge Configration
  57. */
  58. #define CONFIG_SH4_PCI
  59. #define CONFIG_SH7751_PCI
  60. #define CONFIG_PCI_SCAN_SHOW 1
  61. #define __mem_pci
  62. #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
  63. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  64. #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
  65. #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
  66. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  67. #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
  68. #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
  69. #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
  70. #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
  71. #endif /* __CONFIG_H */