p1_p2_rdb_pc.h 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * QorIQ RDB boards configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #if defined(CONFIG_TARGET_P1020MBG)
  11. #define CONFIG_BOARDNAME "P1020MBG-PC"
  12. #define CONFIG_VSC7385_ENET
  13. #define CONFIG_SLIC
  14. #define __SW_BOOT_MASK 0x03
  15. #define __SW_BOOT_NOR 0xe4
  16. #define __SW_BOOT_SD 0x54
  17. #define CONFIG_SYS_L2_SIZE (256 << 10)
  18. #endif
  19. #if defined(CONFIG_TARGET_P1020UTM)
  20. #define CONFIG_BOARDNAME "P1020UTM-PC"
  21. #define __SW_BOOT_MASK 0x03
  22. #define __SW_BOOT_NOR 0xe0
  23. #define __SW_BOOT_SD 0x50
  24. #define CONFIG_SYS_L2_SIZE (256 << 10)
  25. #endif
  26. #if defined(CONFIG_TARGET_P1020RDB_PC)
  27. #define CONFIG_BOARDNAME "P1020RDB-PC"
  28. #define CONFIG_NAND_FSL_ELBC
  29. #define CONFIG_VSC7385_ENET
  30. #define CONFIG_SLIC
  31. #define __SW_BOOT_MASK 0x03
  32. #define __SW_BOOT_NOR 0x5c
  33. #define __SW_BOOT_SPI 0x1c
  34. #define __SW_BOOT_SD 0x9c
  35. #define __SW_BOOT_NAND 0xec
  36. #define __SW_BOOT_PCIE 0x6c
  37. #define CONFIG_SYS_L2_SIZE (256 << 10)
  38. #endif
  39. /*
  40. * P1020RDB-PD board has user selectable switches for evaluating different
  41. * frequency and boot options for the P1020 device. The table that
  42. * follow describe the available options. The front six binary number was in
  43. * accordance with SW3[1:6].
  44. * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  45. * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  46. * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  47. * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  48. * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  49. * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  50. * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  51. */
  52. #if defined(CONFIG_TARGET_P1020RDB_PD)
  53. #define CONFIG_BOARDNAME "P1020RDB-PD"
  54. #define CONFIG_NAND_FSL_ELBC
  55. #define CONFIG_VSC7385_ENET
  56. #define CONFIG_SLIC
  57. #define __SW_BOOT_MASK 0x03
  58. #define __SW_BOOT_NOR 0x64
  59. #define __SW_BOOT_SPI 0x34
  60. #define __SW_BOOT_SD 0x24
  61. #define __SW_BOOT_NAND 0x44
  62. #define __SW_BOOT_PCIE 0x74
  63. #define CONFIG_SYS_L2_SIZE (256 << 10)
  64. /*
  65. * Dynamic MTD Partition support with mtdparts
  66. */
  67. #define CONFIG_MTD_DEVICE
  68. #define CONFIG_MTD_PARTITIONS
  69. #define CONFIG_FLASH_CFI_MTD
  70. #endif
  71. #if defined(CONFIG_TARGET_P1021RDB)
  72. #define CONFIG_BOARDNAME "P1021RDB-PC"
  73. #define CONFIG_NAND_FSL_ELBC
  74. #define CONFIG_QE
  75. #define CONFIG_VSC7385_ENET
  76. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  77. addresses in the LBC */
  78. #define __SW_BOOT_MASK 0x03
  79. #define __SW_BOOT_NOR 0x5c
  80. #define __SW_BOOT_SPI 0x1c
  81. #define __SW_BOOT_SD 0x9c
  82. #define __SW_BOOT_NAND 0xec
  83. #define __SW_BOOT_PCIE 0x6c
  84. #define CONFIG_SYS_L2_SIZE (256 << 10)
  85. /*
  86. * Dynamic MTD Partition support with mtdparts
  87. */
  88. #define CONFIG_MTD_DEVICE
  89. #define CONFIG_MTD_PARTITIONS
  90. #define CONFIG_FLASH_CFI_MTD
  91. #endif
  92. #if defined(CONFIG_TARGET_P1024RDB)
  93. #define CONFIG_BOARDNAME "P1024RDB"
  94. #define CONFIG_NAND_FSL_ELBC
  95. #define CONFIG_SLIC
  96. #define __SW_BOOT_MASK 0xf3
  97. #define __SW_BOOT_NOR 0x00
  98. #define __SW_BOOT_SPI 0x08
  99. #define __SW_BOOT_SD 0x04
  100. #define __SW_BOOT_NAND 0x0c
  101. #define CONFIG_SYS_L2_SIZE (256 << 10)
  102. #endif
  103. #if defined(CONFIG_TARGET_P1025RDB)
  104. #define CONFIG_BOARDNAME "P1025RDB"
  105. #define CONFIG_NAND_FSL_ELBC
  106. #define CONFIG_QE
  107. #define CONFIG_SLIC
  108. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  109. addresses in the LBC */
  110. #define __SW_BOOT_MASK 0xf3
  111. #define __SW_BOOT_NOR 0x00
  112. #define __SW_BOOT_SPI 0x08
  113. #define __SW_BOOT_SD 0x04
  114. #define __SW_BOOT_NAND 0x0c
  115. #define CONFIG_SYS_L2_SIZE (256 << 10)
  116. #endif
  117. #if defined(CONFIG_TARGET_P2020RDB)
  118. #define CONFIG_BOARDNAME "P2020RDB-PC"
  119. #define CONFIG_NAND_FSL_ELBC
  120. #define CONFIG_VSC7385_ENET
  121. #define __SW_BOOT_MASK 0x03
  122. #define __SW_BOOT_NOR 0xc8
  123. #define __SW_BOOT_SPI 0x28
  124. #define __SW_BOOT_SD 0x68 /* or 0x18 */
  125. #define __SW_BOOT_NAND 0xe8
  126. #define __SW_BOOT_PCIE 0xa8
  127. #define CONFIG_SYS_L2_SIZE (512 << 10)
  128. /*
  129. * Dynamic MTD Partition support with mtdparts
  130. */
  131. #define CONFIG_MTD_DEVICE
  132. #define CONFIG_MTD_PARTITIONS
  133. #define CONFIG_FLASH_CFI_MTD
  134. #endif
  135. #ifdef CONFIG_SDCARD
  136. #define CONFIG_SPL_FLUSH_IMAGE
  137. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  138. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  139. #define CONFIG_SPL_PAD_TO 0x20000
  140. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  141. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  142. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  143. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  144. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  145. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  146. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  147. #define CONFIG_SPL_MMC_BOOT
  148. #ifdef CONFIG_SPL_BUILD
  149. #define CONFIG_SPL_COMMON_INIT_DDR
  150. #endif
  151. #endif
  152. #ifdef CONFIG_SPIFLASH
  153. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  154. #define CONFIG_SPL_FLUSH_IMAGE
  155. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  156. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  157. #define CONFIG_SPL_PAD_TO 0x20000
  158. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  159. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  160. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  161. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  162. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  163. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  164. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  165. #define CONFIG_SPL_SPI_BOOT
  166. #ifdef CONFIG_SPL_BUILD
  167. #define CONFIG_SPL_COMMON_INIT_DDR
  168. #endif
  169. #endif
  170. #ifdef CONFIG_NAND
  171. #ifdef CONFIG_TPL_BUILD
  172. #define CONFIG_SPL_NAND_BOOT
  173. #define CONFIG_SPL_FLUSH_IMAGE
  174. #define CONFIG_SPL_NAND_INIT
  175. #define CONFIG_SPL_COMMON_INIT_DDR
  176. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  177. #define CONFIG_SPL_TEXT_BASE 0xf8f81000
  178. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  179. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  180. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  181. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  182. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  183. #elif defined(CONFIG_SPL_BUILD)
  184. #define CONFIG_SPL_INIT_MINIMAL
  185. #define CONFIG_SPL_FLUSH_IMAGE
  186. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  187. #define CONFIG_SPL_TEXT_BASE 0xff800000
  188. #define CONFIG_SPL_MAX_SIZE 4096
  189. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  190. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  191. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  192. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  193. #endif /* not CONFIG_TPL_BUILD */
  194. #define CONFIG_SPL_PAD_TO 0x20000
  195. #define CONFIG_TPL_PAD_TO 0x20000
  196. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  197. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  198. #endif
  199. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  200. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  201. #endif
  202. #ifndef CONFIG_SYS_MONITOR_BASE
  203. #ifdef CONFIG_SPL_BUILD
  204. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  205. #else
  206. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  207. #endif
  208. #endif
  209. #define CONFIG_MP
  210. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  211. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  212. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  213. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  214. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  215. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  216. #define CONFIG_ENV_OVERWRITE
  217. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  218. #define CONFIG_LBA48
  219. #if defined(CONFIG_TARGET_P2020RDB)
  220. #define CONFIG_SYS_CLK_FREQ 100000000
  221. #else
  222. #define CONFIG_SYS_CLK_FREQ 66666666
  223. #endif
  224. #define CONFIG_DDR_CLK_FREQ 66666666
  225. #define CONFIG_HWCONFIG
  226. /*
  227. * These can be toggled for performance analysis, otherwise use default.
  228. */
  229. #define CONFIG_L2_CACHE
  230. #define CONFIG_BTB
  231. #define CONFIG_ENABLE_36BIT_PHYS
  232. #ifdef CONFIG_PHYS_64BIT
  233. #define CONFIG_ADDR_MAP 1
  234. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  235. #endif
  236. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  237. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  238. #define CONFIG_SYS_CCSRBAR 0xffe00000
  239. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  240. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  241. SPL code*/
  242. #ifdef CONFIG_SPL_BUILD
  243. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  244. #endif
  245. /* DDR Setup */
  246. #define CONFIG_SYS_DDR_RAW_TIMING
  247. #define CONFIG_DDR_SPD
  248. #define CONFIG_SYS_SPD_BUS_NUM 1
  249. #define SPD_EEPROM_ADDRESS 0x52
  250. #undef CONFIG_FSL_DDR_INTERACTIVE
  251. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  252. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  253. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  254. #else
  255. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
  256. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  257. #endif
  258. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  259. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  260. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  261. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  262. /* Default settings for DDR3 */
  263. #ifndef CONFIG_TARGET_P2020RDB
  264. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  265. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  266. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  267. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  268. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  269. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  270. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  271. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  272. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  273. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  274. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  275. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  276. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  277. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  278. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  279. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  280. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  281. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  282. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  283. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  284. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  285. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  286. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  287. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  288. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  289. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  290. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  291. #endif
  292. #undef CONFIG_CLOCKS_IN_MHZ
  293. /*
  294. * Memory map
  295. *
  296. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  297. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  298. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  299. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
  300. * (early boot only)
  301. * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
  302. * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
  303. * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
  304. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
  305. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  306. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  307. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  308. */
  309. /*
  310. * Local Bus Definitions
  311. */
  312. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  313. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  314. #define CONFIG_SYS_FLASH_BASE 0xec000000
  315. #elif defined(CONFIG_TARGET_P1020UTM)
  316. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  317. #define CONFIG_SYS_FLASH_BASE 0xee000000
  318. #else
  319. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
  320. #define CONFIG_SYS_FLASH_BASE 0xef000000
  321. #endif
  322. #ifdef CONFIG_PHYS_64BIT
  323. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  324. #else
  325. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  326. #endif
  327. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  328. | BR_PS_16 | BR_V)
  329. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  330. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  331. #define CONFIG_SYS_FLASH_QUIET_TEST
  332. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  333. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  334. #undef CONFIG_SYS_FLASH_CHECKSUM
  335. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  336. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  337. #define CONFIG_FLASH_CFI_DRIVER
  338. #define CONFIG_SYS_FLASH_CFI
  339. #define CONFIG_SYS_FLASH_EMPTY_INFO
  340. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  341. /* Nand Flash */
  342. #ifdef CONFIG_NAND_FSL_ELBC
  343. #define CONFIG_SYS_NAND_BASE 0xff800000
  344. #ifdef CONFIG_PHYS_64BIT
  345. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  346. #else
  347. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  348. #endif
  349. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  350. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  351. #if defined(CONFIG_TARGET_P1020RDB_PD)
  352. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  353. #else
  354. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  355. #endif
  356. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  357. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  358. | BR_PS_8 /* Port Size = 8 bit */ \
  359. | BR_MS_FCM /* MSEL = FCM */ \
  360. | BR_V) /* valid */
  361. #if defined(CONFIG_TARGET_P1020RDB_PD)
  362. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  363. | OR_FCM_PGS /* Large Page*/ \
  364. | OR_FCM_CSCT \
  365. | OR_FCM_CST \
  366. | OR_FCM_CHT \
  367. | OR_FCM_SCY_1 \
  368. | OR_FCM_TRLX \
  369. | OR_FCM_EHTR)
  370. #else
  371. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
  372. | OR_FCM_CSCT \
  373. | OR_FCM_CST \
  374. | OR_FCM_CHT \
  375. | OR_FCM_SCY_1 \
  376. | OR_FCM_TRLX \
  377. | OR_FCM_EHTR)
  378. #endif
  379. #endif /* CONFIG_NAND_FSL_ELBC */
  380. #define CONFIG_SYS_INIT_RAM_LOCK
  381. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  382. #ifdef CONFIG_PHYS_64BIT
  383. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  384. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  385. /* The assembler doesn't like typecast */
  386. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  387. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  388. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  389. #else
  390. /* Initial L1 address */
  391. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  392. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  393. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  394. #endif
  395. /* Size of used area in RAM */
  396. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  397. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  398. GENERATED_GBL_DATA_SIZE)
  399. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  400. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  401. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  402. #define CONFIG_SYS_CPLD_BASE 0xffa00000
  403. #ifdef CONFIG_PHYS_64BIT
  404. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
  405. #else
  406. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  407. #endif
  408. /* CPLD config size: 1Mb */
  409. #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
  410. BR_PS_8 | BR_V)
  411. #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
  412. #define CONFIG_SYS_PMC_BASE 0xff980000
  413. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  414. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  415. BR_PS_8 | BR_V)
  416. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  417. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  418. OR_GPCM_EAD)
  419. #ifdef CONFIG_NAND
  420. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  421. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  422. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  423. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  424. #else
  425. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  426. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  427. #ifdef CONFIG_NAND_FSL_ELBC
  428. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  429. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  430. #endif
  431. #endif
  432. #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
  433. #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
  434. /* Vsc7385 switch */
  435. #ifdef CONFIG_VSC7385_ENET
  436. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  437. #ifdef CONFIG_PHYS_64BIT
  438. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  439. #else
  440. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  441. #endif
  442. #define CONFIG_SYS_VSC7385_BR_PRELIM \
  443. (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
  444. #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
  445. OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
  446. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  447. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
  448. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
  449. /* The size of the VSC7385 firmware image */
  450. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  451. #endif
  452. /*
  453. * Config the L2 Cache as L2 SRAM
  454. */
  455. #if defined(CONFIG_SPL_BUILD)
  456. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  457. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  458. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  459. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  460. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  461. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  462. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  463. #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
  464. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  465. #if defined(CONFIG_TARGET_P2020RDB)
  466. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  467. #else
  468. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  469. #endif
  470. #elif defined(CONFIG_NAND)
  471. #ifdef CONFIG_TPL_BUILD
  472. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  473. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  474. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  475. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  476. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  477. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  478. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  479. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  480. #else
  481. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  482. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  483. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  484. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  485. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  486. #endif /* CONFIG_TPL_BUILD */
  487. #endif
  488. #endif
  489. /* Serial Port - controlled on board with jumper J8
  490. * open - index 2
  491. * shorted - index 1
  492. */
  493. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  494. #define CONFIG_SYS_NS16550_SERIAL
  495. #define CONFIG_SYS_NS16550_REG_SIZE 1
  496. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  497. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  498. #define CONFIG_NS16550_MIN_FUNCTIONS
  499. #endif
  500. #define CONFIG_SYS_BAUDRATE_TABLE \
  501. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  502. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  503. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  504. /* I2C */
  505. #define CONFIG_SYS_I2C
  506. #define CONFIG_SYS_I2C_FSL
  507. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  508. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  509. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  510. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  511. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  512. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  513. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  514. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  515. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  516. /*
  517. * I2C2 EEPROM
  518. */
  519. #undef CONFIG_ID_EEPROM
  520. #define CONFIG_RTC_PT7C4338
  521. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  522. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  523. /* enable read and write access to EEPROM */
  524. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  525. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  526. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  527. /*
  528. * eSPI - Enhanced SPI
  529. */
  530. #define CONFIG_HARD_SPI
  531. #if defined(CONFIG_SPI_FLASH)
  532. #define CONFIG_SF_DEFAULT_SPEED 10000000
  533. #define CONFIG_SF_DEFAULT_MODE 0
  534. #endif
  535. #if defined(CONFIG_PCI)
  536. /*
  537. * General PCI
  538. * Memory space is mapped 1-1, but I/O space must start from 0.
  539. */
  540. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  541. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
  542. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  543. #ifdef CONFIG_PHYS_64BIT
  544. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  545. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  546. #else
  547. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  548. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  549. #endif
  550. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  551. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  552. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  553. #ifdef CONFIG_PHYS_64BIT
  554. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  555. #else
  556. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  557. #endif
  558. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  559. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  560. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  561. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  562. #ifdef CONFIG_PHYS_64BIT
  563. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  564. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  565. #else
  566. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  567. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  568. #endif
  569. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  570. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  571. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  572. #ifdef CONFIG_PHYS_64BIT
  573. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  574. #else
  575. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  576. #endif
  577. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  578. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  579. #endif /* CONFIG_PCI */
  580. #if defined(CONFIG_TSEC_ENET)
  581. #define CONFIG_MII /* MII PHY management */
  582. #define CONFIG_TSEC1
  583. #define CONFIG_TSEC1_NAME "eTSEC1"
  584. #define CONFIG_TSEC2
  585. #define CONFIG_TSEC2_NAME "eTSEC2"
  586. #define CONFIG_TSEC3
  587. #define CONFIG_TSEC3_NAME "eTSEC3"
  588. #define TSEC1_PHY_ADDR 2
  589. #define TSEC2_PHY_ADDR 0
  590. #define TSEC3_PHY_ADDR 1
  591. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  592. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  593. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  594. #define TSEC1_PHYIDX 0
  595. #define TSEC2_PHYIDX 0
  596. #define TSEC3_PHYIDX 0
  597. #define CONFIG_ETHPRIME "eTSEC1"
  598. #define CONFIG_HAS_ETH0
  599. #define CONFIG_HAS_ETH1
  600. #define CONFIG_HAS_ETH2
  601. #endif /* CONFIG_TSEC_ENET */
  602. #ifdef CONFIG_QE
  603. /* QE microcode/firmware address */
  604. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  605. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  606. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  607. #endif /* CONFIG_QE */
  608. #ifdef CONFIG_TARGET_P1025RDB
  609. /*
  610. * QE UEC ethernet configuration
  611. */
  612. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  613. #undef CONFIG_UEC_ETH
  614. #define CONFIG_PHY_MODE_NEED_CHANGE
  615. #define CONFIG_UEC_ETH1 /* ETH1 */
  616. #define CONFIG_HAS_ETH0
  617. #ifdef CONFIG_UEC_ETH1
  618. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  619. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
  620. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
  621. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  622. #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
  623. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  624. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  625. #endif /* CONFIG_UEC_ETH1 */
  626. #define CONFIG_UEC_ETH5 /* ETH5 */
  627. #define CONFIG_HAS_ETH1
  628. #ifdef CONFIG_UEC_ETH5
  629. #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
  630. #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
  631. #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
  632. #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
  633. #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
  634. #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  635. #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
  636. #endif /* CONFIG_UEC_ETH5 */
  637. #endif /* CONFIG_TARGET_P1025RDB */
  638. /*
  639. * Environment
  640. */
  641. #ifdef CONFIG_SPIFLASH
  642. #define CONFIG_ENV_SPI_BUS 0
  643. #define CONFIG_ENV_SPI_CS 0
  644. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  645. #define CONFIG_ENV_SPI_MODE 0
  646. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  647. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  648. #define CONFIG_ENV_SECT_SIZE 0x10000
  649. #elif defined(CONFIG_SDCARD)
  650. #define CONFIG_FSL_FIXED_MMC_LOCATION
  651. #define CONFIG_ENV_SIZE 0x2000
  652. #define CONFIG_SYS_MMC_ENV_DEV 0
  653. #elif defined(CONFIG_NAND)
  654. #ifdef CONFIG_TPL_BUILD
  655. #define CONFIG_ENV_SIZE 0x2000
  656. #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  657. #else
  658. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  659. #endif
  660. #define CONFIG_ENV_OFFSET (1024 * 1024)
  661. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  662. #elif defined(CONFIG_SYS_RAMBOOT)
  663. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  664. #define CONFIG_ENV_SIZE 0x2000
  665. #else
  666. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  667. #define CONFIG_ENV_SIZE 0x2000
  668. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  669. #endif
  670. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  671. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  672. /*
  673. * USB
  674. */
  675. #define CONFIG_HAS_FSL_DR_USB
  676. #if defined(CONFIG_HAS_FSL_DR_USB)
  677. #ifdef CONFIG_USB_EHCI_HCD
  678. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  679. #define CONFIG_USB_EHCI_FSL
  680. #define CONFIG_EHCI_DESC_BIG_ENDIAN
  681. #endif
  682. #endif
  683. #if defined(CONFIG_TARGET_P1020RDB_PD)
  684. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  685. #endif
  686. #ifdef CONFIG_MMC
  687. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  688. #endif
  689. #undef CONFIG_WATCHDOG /* watchdog disabled */
  690. /*
  691. * Miscellaneous configurable options
  692. */
  693. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  694. /*
  695. * For booting Linux, the board info and command line data
  696. * have to be in the first 64 MB of memory, since this is
  697. * the maximum mapped by the Linux kernel during initialization.
  698. */
  699. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  700. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  701. #if defined(CONFIG_CMD_KGDB)
  702. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  703. #endif
  704. /*
  705. * Environment Configuration
  706. */
  707. #define CONFIG_HOSTNAME "unknown"
  708. #define CONFIG_ROOTPATH "/opt/nfsroot"
  709. #define CONFIG_BOOTFILE "uImage"
  710. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  711. /* default location for tftp and bootm */
  712. #define CONFIG_LOADADDR 1000000
  713. #ifdef __SW_BOOT_NOR
  714. #define __NOR_RST_CMD \
  715. norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
  716. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  717. #endif
  718. #ifdef __SW_BOOT_SPI
  719. #define __SPI_RST_CMD \
  720. spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
  721. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  722. #endif
  723. #ifdef __SW_BOOT_SD
  724. #define __SD_RST_CMD \
  725. sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
  726. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  727. #endif
  728. #ifdef __SW_BOOT_NAND
  729. #define __NAND_RST_CMD \
  730. nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
  731. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  732. #endif
  733. #ifdef __SW_BOOT_PCIE
  734. #define __PCIE_RST_CMD \
  735. pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
  736. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  737. #endif
  738. #define CONFIG_EXTRA_ENV_SETTINGS \
  739. "netdev=eth0\0" \
  740. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  741. "loadaddr=1000000\0" \
  742. "bootfile=uImage\0" \
  743. "tftpflash=tftpboot $loadaddr $uboot; " \
  744. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  745. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  746. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  747. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  748. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  749. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  750. "consoledev=ttyS0\0" \
  751. "ramdiskaddr=2000000\0" \
  752. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  753. "fdtaddr=1e00000\0" \
  754. "bdev=sda1\0" \
  755. "jffs2nor=mtdblock3\0" \
  756. "norbootaddr=ef080000\0" \
  757. "norfdtaddr=ef040000\0" \
  758. "jffs2nand=mtdblock9\0" \
  759. "nandbootaddr=100000\0" \
  760. "nandfdtaddr=80000\0" \
  761. "ramdisk_size=120000\0" \
  762. "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
  763. "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
  764. __stringify(__NOR_RST_CMD)"\0" \
  765. __stringify(__SPI_RST_CMD)"\0" \
  766. __stringify(__SD_RST_CMD)"\0" \
  767. __stringify(__NAND_RST_CMD)"\0" \
  768. __stringify(__PCIE_RST_CMD)"\0"
  769. #define CONFIG_NFSBOOTCOMMAND \
  770. "setenv bootargs root=/dev/nfs rw " \
  771. "nfsroot=$serverip:$rootpath " \
  772. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  773. "console=$consoledev,$baudrate $othbootargs;" \
  774. "tftp $loadaddr $bootfile;" \
  775. "tftp $fdtaddr $fdtfile;" \
  776. "bootm $loadaddr - $fdtaddr"
  777. #define CONFIG_HDBOOT \
  778. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  779. "console=$consoledev,$baudrate $othbootargs;" \
  780. "usb start;" \
  781. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  782. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  783. "bootm $loadaddr - $fdtaddr"
  784. #define CONFIG_USB_FAT_BOOT \
  785. "setenv bootargs root=/dev/ram rw " \
  786. "console=$consoledev,$baudrate $othbootargs " \
  787. "ramdisk_size=$ramdisk_size;" \
  788. "usb start;" \
  789. "fatload usb 0:2 $loadaddr $bootfile;" \
  790. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  791. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  792. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  793. #define CONFIG_USB_EXT2_BOOT \
  794. "setenv bootargs root=/dev/ram rw " \
  795. "console=$consoledev,$baudrate $othbootargs " \
  796. "ramdisk_size=$ramdisk_size;" \
  797. "usb start;" \
  798. "ext2load usb 0:4 $loadaddr $bootfile;" \
  799. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  800. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  801. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  802. #define CONFIG_NORBOOT \
  803. "setenv bootargs root=/dev/$jffs2nor rw " \
  804. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  805. "bootm $norbootaddr - $norfdtaddr"
  806. #define CONFIG_RAMBOOTCOMMAND \
  807. "setenv bootargs root=/dev/ram rw " \
  808. "console=$consoledev,$baudrate $othbootargs " \
  809. "ramdisk_size=$ramdisk_size;" \
  810. "tftp $ramdiskaddr $ramdiskfile;" \
  811. "tftp $loadaddr $bootfile;" \
  812. "tftp $fdtaddr $fdtfile;" \
  813. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  814. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  815. #endif /* __CONFIG_H */