omapl138_lcdk.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on davinci_dvevm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * Board
  13. */
  14. #define CONFIG_DRIVER_TI_EMAC
  15. #undef CONFIG_USE_SPIFLASH
  16. #undef CONFIG_SYS_USE_NOR
  17. #define CONFIG_USE_NAND
  18. /*
  19. * Disable DM_* for SPL build and can be re-enabled after adding
  20. * DM support in SPL
  21. */
  22. #ifdef CONFIG_SPL_BUILD
  23. #undef CONFIG_DM_I2C
  24. #undef CONFIG_DM_I2C_COMPAT
  25. #endif
  26. /*
  27. * SoC Configuration
  28. */
  29. #define CONFIG_MACH_OMAPL138_LCDK
  30. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  31. #define CONFIG_SYS_OSCIN_FREQ 24000000
  32. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  33. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  34. #define CONFIG_SYS_HZ 1000
  35. #define CONFIG_SKIP_LOWLEVEL_INIT
  36. /*
  37. * Memory Info
  38. */
  39. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  40. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  41. #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
  42. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  43. /* memtest start addr */
  44. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  45. /* memtest will be run on 16MB */
  46. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  47. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  48. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  49. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  50. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  51. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  52. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  53. DAVINCI_SYSCFG_SUSPSRC_I2C)
  54. /*
  55. * PLL configuration
  56. */
  57. /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  58. #define CONFIG_SYS_DA850_PLL0_PLLM 18
  59. #define CONFIG_SYS_DA850_PLL1_PLLM 21
  60. /*
  61. * DDR2 memory configuration
  62. */
  63. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  64. DV_DDR_PHY_EXT_STRBEN | \
  65. (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  66. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  67. (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
  68. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  69. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  70. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  71. (4 << DV_DDR_SDCR_CL_SHIFT) | \
  72. (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
  73. (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  74. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  75. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  76. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  77. (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  78. (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
  79. (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  80. (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
  81. (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  82. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  83. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  84. (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  85. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  86. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  87. (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
  88. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  89. (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  90. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  91. (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  92. (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  93. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
  94. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  95. /*
  96. * Serial Driver info
  97. */
  98. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  99. #if !defined(CONFIG_DM_SERIAL)
  100. #define CONFIG_SYS_NS16550_SERIAL
  101. #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
  102. #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
  103. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  104. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  105. #endif
  106. #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
  107. #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
  108. #define CONFIG_SF_DEFAULT_SPEED 30000000
  109. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  110. #ifdef CONFIG_USE_SPIFLASH
  111. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
  112. #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
  113. #endif
  114. /*
  115. * I2C Configuration
  116. */
  117. #define CONFIG_SYS_I2C_DAVINCI
  118. #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
  119. #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
  120. #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
  121. /*
  122. * Flash & Environment
  123. */
  124. #ifdef CONFIG_USE_NAND
  125. #define CONFIG_NAND_DAVINCI
  126. #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
  127. #define CONFIG_ENV_SIZE (128 << 9)
  128. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  129. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  130. #define CONFIG_SYS_NAND_PAGE_2K
  131. #define CONFIG_SYS_NAND_CS 3
  132. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  133. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  134. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  135. #undef CONFIG_SYS_NAND_HW_ECC
  136. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  137. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  138. #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  139. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  140. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  141. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  142. #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
  143. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  144. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  145. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  146. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  147. CONFIG_SYS_MALLOC_LEN - \
  148. GENERATED_GBL_DATA_SIZE)
  149. #define CONFIG_SYS_NAND_ECCPOS { \
  150. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
  151. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
  152. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
  153. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
  154. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  155. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  156. #define CONFIG_SYS_NAND_ECCSIZE 512
  157. #define CONFIG_SYS_NAND_ECCBYTES 10
  158. #define CONFIG_SYS_NAND_OOBSIZE 64
  159. #define CONFIG_SPL_NAND_BASE
  160. #define CONFIG_SPL_NAND_DRIVERS
  161. #define CONFIG_SPL_NAND_ECC
  162. #define CONFIG_SPL_NAND_LOAD
  163. #endif
  164. #ifdef CONFIG_SYS_USE_NOR
  165. #define CONFIG_FLASH_CFI_DRIVER
  166. #define CONFIG_SYS_FLASH_CFI
  167. #define CONFIG_SYS_FLASH_PROTECTION
  168. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  169. #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
  170. #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
  171. #define CONFIG_ENV_SIZE (128 << 10)
  172. #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
  173. #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
  174. #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
  175. + 3)
  176. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
  177. #endif
  178. #ifdef CONFIG_USE_SPIFLASH
  179. #define CONFIG_ENV_SIZE (64 << 10)
  180. #define CONFIG_ENV_OFFSET (256 << 10)
  181. #define CONFIG_ENV_SECT_SIZE (64 << 10)
  182. #endif
  183. /*
  184. * Network & Ethernet Configuration
  185. */
  186. #ifdef CONFIG_DRIVER_TI_EMAC
  187. #define CONFIG_MII
  188. #undef CONFIG_DRIVER_TI_EMAC_USE_RMII
  189. #define CONFIG_BOOTP_DEFAULT
  190. #define CONFIG_BOOTP_DNS2
  191. #define CONFIG_BOOTP_SEND_HOSTNAME
  192. #define CONFIG_NET_RETRY_COUNT 10
  193. #endif
  194. /*
  195. * U-Boot general configuration
  196. */
  197. #define CONFIG_MISC_INIT_R
  198. #define CONFIG_BOOTFILE "zImage" /* Boot file name */
  199. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  200. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  201. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  202. #define CONFIG_MX_CYCLIC
  203. /*
  204. * Linux Information
  205. */
  206. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  207. #define CONFIG_CMDLINE_TAG
  208. #define CONFIG_REVISION_TAG
  209. #define CONFIG_SETUP_MEMORY_TAGS
  210. #define CONFIG_BOOTCOMMAND \
  211. "run envboot; " \
  212. "run mmcboot; "
  213. #define DEFAULT_LINUX_BOOT_ENV \
  214. "loadaddr=0xc0700000\0" \
  215. "fdtaddr=0xc0600000\0" \
  216. "scriptaddr=0xc0600000\0"
  217. #include <environment/ti/mmc.h>
  218. #define CONFIG_EXTRA_ENV_SETTINGS \
  219. DEFAULT_LINUX_BOOT_ENV \
  220. DEFAULT_MMC_TI_ARGS \
  221. "bootpart=0:2\0" \
  222. "bootdir=/boot\0" \
  223. "bootfile=zImage\0" \
  224. "fdtfile=da850-lcdk.dtb\0" \
  225. "boot_fdt=yes\0" \
  226. "boot_fit=0\0" \
  227. "console=ttyS2,115200n8\0"
  228. #ifdef CONFIG_CMD_BDI
  229. #define CONFIG_CLOCKS
  230. #endif
  231. #ifndef CONFIG_DRIVER_TI_EMAC
  232. #endif
  233. #ifdef CONFIG_USE_NAND
  234. #define CONFIG_MTD_DEVICE
  235. #define CONFIG_MTD_PARTITIONS
  236. #endif
  237. #if !defined(CONFIG_USE_NAND) && \
  238. !defined(CONFIG_SYS_USE_NOR) && \
  239. !defined(CONFIG_USE_SPIFLASH)
  240. #define CONFIG_ENV_SIZE (16 << 10)
  241. #endif
  242. /* SD/MMC */
  243. #ifdef CONFIG_ENV_IS_IN_MMC
  244. #undef CONFIG_ENV_SIZE
  245. #undef CONFIG_ENV_OFFSET
  246. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  247. #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
  248. #endif
  249. #ifndef CONFIG_DIRECT_NOR_BOOT
  250. /* defines for SPL */
  251. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  252. CONFIG_SYS_MALLOC_LEN)
  253. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  254. #define CONFIG_SPL_STACK 0x8001ff00
  255. #define CONFIG_SPL_TEXT_BASE 0x80000000
  256. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  257. #define CONFIG_SPL_PAD_TO 32768
  258. #endif
  259. /* additions for new relocation code, must added to all boards */
  260. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  261. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  262. GENERATED_GBL_DATA_SIZE)
  263. #include <asm/arch/hardware.h>
  264. #endif /* __CONFIG_H */