ms7720se.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Hitachi Solution Engine 7720
  4. *
  5. * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  6. */
  7. #ifndef __MS7720SE_H
  8. #define __MS7720SE_H
  9. #define CONFIG_CPU_SH7720 1
  10. #define CONFIG_BOOTFILE "/boot/zImage"
  11. #define CONFIG_LOADADDR 0x8E000000
  12. #define CONFIG_DISPLAY_BOARDINFO
  13. #undef CONFIG_SHOW_BOOT_PROGRESS
  14. /* MEMORY */
  15. #define MS7720SE_SDRAM_BASE 0x8C000000
  16. #define MS7720SE_FLASH_BASE_1 0xA0000000
  17. #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
  18. #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
  19. /* List of legal baudrate settings for this board */
  20. #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  21. /* SCIF */
  22. #define CONFIG_CONS_SCIF0 1
  23. #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
  24. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  25. #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
  26. #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
  27. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  28. #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
  29. #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
  30. #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
  31. #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  32. /* FLASH */
  33. #define CONFIG_SYS_FLASH_CFI
  34. #define CONFIG_FLASH_CFI_DRIVER
  35. #undef CONFIG_SYS_FLASH_QUIET_TEST
  36. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  37. #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
  38. #define CONFIG_SYS_MAX_FLASH_SECT 150
  39. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  40. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  41. #define CONFIG_ENV_SECT_SIZE (64 * 1024)
  42. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  43. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  44. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
  45. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  46. /* Board Clock */
  47. #define CONFIG_SYS_CLK_FREQ 33333333
  48. #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  49. #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  50. #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
  51. /* PCMCIA */
  52. #define CONFIG_IDE_PCMCIA 1
  53. #define CONFIG_MARUBUN_PCCARD 1
  54. #define CONFIG_PCMCIA_SLOT_A 1
  55. #define CONFIG_SYS_IDE_MAXDEVICE 1
  56. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
  57. #define CONFIG_SYS_MARUBUN_MW1 0xb8400000
  58. #define CONFIG_SYS_MARUBUN_MW2 0xb8500000
  59. #define CONFIG_SYS_MARUBUN_IO 0xb8600000
  60. #define CONFIG_SYS_PIO_MODE 1
  61. #define CONFIG_SYS_IDE_MAXBUS 1
  62. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
  63. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
  64. #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
  65. #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
  66. #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  67. #define CONFIG_IDE_SWAP_IO
  68. #endif /* __MS7720SE_H */