mcx.h 9.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
  4. *
  5. * Based on omap3_evm_config.h
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_MACH_TYPE MACH_TYPE_MCX
  13. #include <asm/arch/cpu.h> /* get chip and board defs */
  14. #include <asm/arch/omap.h>
  15. /*
  16. * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
  17. * and older u-boot.bin with the new U-Boot SPL.
  18. */
  19. /* Clock Defines */
  20. #define V_OSCK 26000000 /* Clock output from T2 */
  21. #define V_SCLK (V_OSCK >> 1)
  22. #define CONFIG_MISC_INIT_R
  23. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  24. #define CONFIG_SETUP_MEMORY_TAGS
  25. #define CONFIG_INITRD_TAG
  26. #define CONFIG_REVISION_TAG
  27. /*
  28. * Size of malloc() pool
  29. */
  30. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
  31. #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
  32. /*
  33. * DDR related
  34. */
  35. #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
  36. /*
  37. * Hardware drivers
  38. */
  39. /*
  40. * NS16550 Configuration
  41. */
  42. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  43. #define CONFIG_SYS_NS16550_SERIAL
  44. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  45. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  46. /*
  47. * select serial console configuration
  48. */
  49. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  50. #define CONFIG_SERIAL3 3 /* UART3 */
  51. /* allow to overwrite serial and ethaddr */
  52. #define CONFIG_ENV_OVERWRITE
  53. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  54. 115200}
  55. /* EHCI */
  56. #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
  57. /* commands to include */
  58. #define CONFIG_MTD_PARTITIONS
  59. #define CONFIG_MTD_DEVICE
  60. #define CONFIG_SYS_I2C
  61. /* RTC */
  62. #define CONFIG_RTC_DS1337
  63. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  64. /*
  65. * Board NAND Info.
  66. */
  67. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  68. /* to access nand */
  69. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  70. /* to access */
  71. /* nand at CS0 */
  72. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  73. /* NAND devices */
  74. #define CONFIG_JFFS2_NAND
  75. /* nand device jffs2 lives on */
  76. #define CONFIG_JFFS2_DEV "nand0"
  77. /* start of jffs2 partition */
  78. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  79. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
  80. /* Environment information */
  81. #define CONFIG_BOOTFILE "uImage"
  82. /* Setup MTD for NAND on the SOM */
  83. #define CONFIG_HOSTNAME "mcx"
  84. #define CONFIG_EXTRA_ENV_SETTINGS \
  85. "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
  86. "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
  87. "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
  88. "addfb=setenv bootargs ${bootargs} vram=6M " \
  89. "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
  90. "addip_sta=setenv bootargs ${bootargs} " \
  91. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  92. "${netmask}:${hostname}:eth0:off\0" \
  93. "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
  94. "addip=if test -n ${ipdyn};then run addip_dyn;" \
  95. "else run addip_sta;fi\0" \
  96. "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
  97. "addtty=setenv bootargs ${bootargs} " \
  98. "console=${consoledev},${baudrate}\0" \
  99. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  100. "baudrate=115200\0" \
  101. "consoledev=ttyO2\0" \
  102. "hostname=" CONFIG_HOSTNAME "\0" \
  103. "loadaddr=0x82000000\0" \
  104. "load=tftp ${loadaddr} ${u-boot}\0" \
  105. "load_k=tftp ${loadaddr} ${bootfile}\0" \
  106. "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
  107. "loadmlo=tftp ${loadaddr} ${mlo}\0" \
  108. "mlo=" CONFIG_HOSTNAME "/MLO\0" \
  109. "mmcargs=root=/dev/mmcblk0p2 rw " \
  110. "rootfstype=ext3 rootwait\0" \
  111. "mmcboot=echo Booting from mmc ...; " \
  112. "run mmcargs; " \
  113. "run addip addtty addmtd addfb addeth addmisc;" \
  114. "run loaduimage; " \
  115. "bootm ${loadaddr}\0" \
  116. "net_nfs=run load_k; " \
  117. "run nfsargs; " \
  118. "run addip addtty addmtd addfb addeth addmisc;" \
  119. "bootm ${loadaddr}\0" \
  120. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  121. "nfsroot=${serverip}:${rootpath}\0" \
  122. "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
  123. "uboot_addr=0x80000\0" \
  124. "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
  125. "nand write ${loadaddr} ${uboot_addr} 80000\0" \
  126. "updatemlo=nandecc hw;nand erase 0 20000;" \
  127. "nand write ${loadaddr} 0 20000\0" \
  128. "upd=if run load;then echo Updating u-boot;if run update;" \
  129. "then echo U-Boot updated;" \
  130. "else echo Error updating u-boot !;" \
  131. "echo Board without bootloader !!;" \
  132. "fi;" \
  133. "else echo U-Boot not downloaded..exiting;fi\0" \
  134. "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
  135. "bootscript=echo Running bootscript from mmc ...; " \
  136. "source ${loadaddr}\0" \
  137. "nandargs=setenv bootargs ubi.mtd=7 " \
  138. "root=ubi0:rootfs rootfstype=ubifs\0" \
  139. "nandboot=echo Booting from nand ...; " \
  140. "run nandargs; " \
  141. "ubi part nand0,4;" \
  142. "ubi readvol ${loadaddr} kernel;" \
  143. "run addtty addmtd addfb addeth addmisc;" \
  144. "bootm ${loadaddr}\0" \
  145. "preboot=ubi part nand0,7;" \
  146. "ubi readvol ${loadaddr} splash;" \
  147. "bmp display ${loadaddr};" \
  148. "gpio set 55\0" \
  149. "swupdate_args=setenv bootargs root=/dev/ram " \
  150. "quiet loglevel=1 " \
  151. "consoleblank=0 ${swupdate_misc}\0" \
  152. "swupdate=echo Running Sw-Update...;" \
  153. "if printenv mtdparts;then echo Starting SwUpdate...; " \
  154. "else mtdparts default;fi; " \
  155. "ubi part nand0,5;" \
  156. "ubi readvol 0x82000000 kernel_recovery;" \
  157. "ubi part nand0,6;" \
  158. "ubi readvol 0x84000000 fs_recovery;" \
  159. "run swupdate_args; " \
  160. "setenv bootargs ${bootargs} " \
  161. "${mtdparts} " \
  162. "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
  163. "omapdss.def_disp=lcd;" \
  164. "bootm 0x82000000 0x84000000\0" \
  165. "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
  166. "then source 82000000;else run nandboot;fi\0"
  167. /*
  168. * Miscellaneous configurable options
  169. */
  170. #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
  171. /* Boot Argument Buffer Size */
  172. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  173. /* memtest works on */
  174. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  175. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  176. 0x01F00000) /* 31MB */
  177. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  178. /* address */
  179. #define CONFIG_PREBOOT
  180. /*
  181. * AM3517 has 12 GP timers, they can be driven by the system clock
  182. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  183. * This rate is divided by a local divisor.
  184. */
  185. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  186. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  187. /*
  188. * Physical Memory Map
  189. */
  190. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  191. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  192. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  193. /*
  194. * FLASH and environment organization
  195. */
  196. /* **** PISMO SUPPORT *** */
  197. /* Redundant Environment */
  198. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
  199. #define CONFIG_ENV_OFFSET 0x180000
  200. #define CONFIG_ENV_ADDR 0x180000
  201. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
  202. 2 * CONFIG_SYS_ENV_SECT_SIZE)
  203. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  204. /* Flash banks JFFS2 should use */
  205. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  206. CONFIG_SYS_MAX_NAND_DEVICE)
  207. #define CONFIG_SYS_JFFS2_MEM_NAND
  208. /* use flash_info[2] */
  209. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  210. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  211. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  212. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  213. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  214. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  215. CONFIG_SYS_INIT_RAM_SIZE - \
  216. GENERATED_GBL_DATA_SIZE)
  217. /* Defines for SPL */
  218. #define CONFIG_SPL_NAND_BASE
  219. #define CONFIG_SPL_NAND_DRIVERS
  220. #define CONFIG_SPL_NAND_ECC
  221. #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
  222. #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
  223. #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  224. /* move malloc and bss high to prevent clashing with the main image */
  225. #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
  226. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  227. #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
  228. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  229. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  230. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  231. /* NAND boot config */
  232. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  233. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  234. #define CONFIG_SYS_NAND_OOBSIZE 64
  235. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  236. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  237. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  238. #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
  239. 48, 49, 50, 51, 52, 53, 54, 55,\
  240. 56, 57, 58, 59, 60, 61, 62, 63}
  241. #define CONFIG_SYS_NAND_ECCSIZE 256
  242. #define CONFIG_SYS_NAND_ECCBYTES 3
  243. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
  244. #define CONFIG_SPL_NAND_SOFTECC
  245. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  246. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  247. /*
  248. * ethernet support
  249. *
  250. */
  251. #if defined(CONFIG_CMD_NET)
  252. #define CONFIG_DRIVER_TI_EMAC
  253. #define CONFIG_DRIVER_TI_EMAC_USE_RMII
  254. #define CONFIG_MII
  255. #define CONFIG_BOOTP_DNS2
  256. #define CONFIG_BOOTP_SEND_HOSTNAME
  257. #define CONFIG_NET_RETRY_COUNT 10
  258. #endif
  259. #define CONFIG_SPLASH_SCREEN
  260. #define CONFIG_VIDEO_BMP_RLE8
  261. #define CONFIG_VIDEO_OMAP3
  262. #endif /* __CONFIG_H */