ls2080aqds.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_QDS_H
  7. #define __LS2_QDS_H
  8. #include "ls2080a_common.h"
  9. #ifndef __ASSEMBLY__
  10. unsigned long get_board_sys_clk(void);
  11. unsigned long get_board_ddr_clk(void);
  12. #endif
  13. #ifdef CONFIG_FSL_QSPI
  14. #define CONFIG_QIXIS_I2C_ACCESS
  15. #define CONFIG_SYS_I2C_EARLY_INIT
  16. #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
  17. #endif
  18. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  19. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  20. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  21. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  22. #define CONFIG_DDR_SPD
  23. #define CONFIG_DDR_ECC
  24. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  25. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  26. #define SPD_EEPROM_ADDRESS1 0x51
  27. #define SPD_EEPROM_ADDRESS2 0x52
  28. #define SPD_EEPROM_ADDRESS3 0x53
  29. #define SPD_EEPROM_ADDRESS4 0x54
  30. #define SPD_EEPROM_ADDRESS5 0x55
  31. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  32. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  33. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  34. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  35. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  36. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  37. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  38. #endif
  39. #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
  40. /* SATA */
  41. #define CONFIG_SCSI_AHCI_PLAT
  42. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  43. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  44. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  45. #define CONFIG_SYS_SCSI_MAX_LUN 1
  46. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  47. CONFIG_SYS_SCSI_MAX_LUN)
  48. /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  49. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  50. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  51. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  52. #define CONFIG_SYS_NOR0_CSPR \
  53. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  54. CSPR_PORT_SIZE_16 | \
  55. CSPR_MSEL_NOR | \
  56. CSPR_V)
  57. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  58. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  59. CSPR_PORT_SIZE_16 | \
  60. CSPR_MSEL_NOR | \
  61. CSPR_V)
  62. #define CONFIG_SYS_NOR1_CSPR \
  63. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
  64. CSPR_PORT_SIZE_16 | \
  65. CSPR_MSEL_NOR | \
  66. CSPR_V)
  67. #define CONFIG_SYS_NOR1_CSPR_EARLY \
  68. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  69. CSPR_PORT_SIZE_16 | \
  70. CSPR_MSEL_NOR | \
  71. CSPR_V)
  72. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  73. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  74. FTIM0_NOR_TEADC(0x5) | \
  75. FTIM0_NOR_TEAHC(0x5))
  76. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  77. FTIM1_NOR_TRAD_NOR(0x1a) |\
  78. FTIM1_NOR_TSEQRAD_NOR(0x13))
  79. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  80. FTIM2_NOR_TCH(0x4) | \
  81. FTIM2_NOR_TWPH(0x0E) | \
  82. FTIM2_NOR_TWP(0x1c))
  83. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  84. #define CONFIG_SYS_IFC_CCR 0x01000000
  85. #ifdef CONFIG_MTD_NOR_FLASH
  86. #define CONFIG_FLASH_CFI_DRIVER
  87. #define CONFIG_SYS_FLASH_CFI
  88. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  89. #define CONFIG_SYS_FLASH_QUIET_TEST
  90. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  91. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  92. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  93. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  94. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  95. #define CONFIG_SYS_FLASH_EMPTY_INFO
  96. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  97. CONFIG_SYS_FLASH_BASE + 0x40000000}
  98. #endif
  99. #define CONFIG_NAND_FSL_IFC
  100. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  101. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  102. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  103. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  104. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  105. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  106. | CSPR_V)
  107. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  108. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  109. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  110. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  111. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  112. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  113. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  114. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  115. #define CONFIG_SYS_NAND_ONFI_DETECTION
  116. /* ONFI NAND Flash mode0 Timing Params */
  117. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  118. FTIM0_NAND_TWP(0x18) | \
  119. FTIM0_NAND_TWCHT(0x07) | \
  120. FTIM0_NAND_TWH(0x0a))
  121. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  122. FTIM1_NAND_TWBE(0x39) | \
  123. FTIM1_NAND_TRR(0x0e) | \
  124. FTIM1_NAND_TRP(0x18))
  125. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  126. FTIM2_NAND_TREH(0x0a) | \
  127. FTIM2_NAND_TWHRE(0x1e))
  128. #define CONFIG_SYS_NAND_FTIM3 0x0
  129. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  130. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  131. #define CONFIG_MTD_NAND_VERIFY_WRITE
  132. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  133. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  134. #define QIXIS_LBMAP_SWITCH 0x06
  135. #define QIXIS_LBMAP_MASK 0x0f
  136. #define QIXIS_LBMAP_SHIFT 0
  137. #define QIXIS_LBMAP_DFLTBANK 0x00
  138. #define QIXIS_LBMAP_ALTBANK 0x04
  139. #define QIXIS_LBMAP_NAND 0x09
  140. #define QIXIS_LBMAP_SD 0x00
  141. #define QIXIS_LBMAP_QSPI 0x0f
  142. #define QIXIS_RST_CTL_RESET 0x31
  143. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  144. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  145. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  146. #define QIXIS_RCW_SRC_NAND 0x107
  147. #define QIXIS_RCW_SRC_SD 0x40
  148. #define QIXIS_RCW_SRC_QSPI 0x62
  149. #define QIXIS_RST_FORCE_MEM 0x01
  150. #define CONFIG_SYS_CSPR3_EXT (0x0)
  151. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  152. | CSPR_PORT_SIZE_8 \
  153. | CSPR_MSEL_GPCM \
  154. | CSPR_V)
  155. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  156. | CSPR_PORT_SIZE_8 \
  157. | CSPR_MSEL_GPCM \
  158. | CSPR_V)
  159. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  160. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  161. /* QIXIS Timing parameters for IFC CS3 */
  162. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  163. FTIM0_GPCM_TEADC(0x0e) | \
  164. FTIM0_GPCM_TEAHC(0x0e))
  165. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  166. FTIM1_GPCM_TRAD(0x3f))
  167. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  168. FTIM2_GPCM_TCH(0xf) | \
  169. FTIM2_GPCM_TWP(0x3E))
  170. #define CONFIG_SYS_CS3_FTIM3 0x0
  171. #if defined(CONFIG_SPL)
  172. #if defined(CONFIG_NAND_BOOT)
  173. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  174. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
  175. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
  176. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  177. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  178. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  179. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  180. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  181. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  182. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  183. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
  184. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
  185. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
  186. #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
  187. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  188. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  189. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  190. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  191. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  192. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  193. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  194. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  195. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  196. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  197. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  198. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  199. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  200. #define CONFIG_ENV_OFFSET (896 * 1024)
  201. #define CONFIG_ENV_SECT_SIZE 0x20000
  202. #define CONFIG_ENV_SIZE 0x2000
  203. #define CONFIG_SPL_PAD_TO 0x20000
  204. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
  205. #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
  206. #elif defined(CONFIG_SD_BOOT)
  207. #define CONFIG_ENV_OFFSET 0x300000
  208. #define CONFIG_SYS_MMC_ENV_DEV 0
  209. #define CONFIG_ENV_SIZE 0x20000
  210. #endif
  211. #else
  212. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  213. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  214. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  215. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  216. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  217. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  218. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  219. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  220. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  221. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  222. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  223. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  224. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  225. #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  226. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  227. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  228. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  229. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  230. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  231. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  232. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  233. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  234. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  235. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  236. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  237. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  238. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  239. #ifndef CONFIG_QSPI_BOOT
  240. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
  241. #define CONFIG_ENV_SECT_SIZE 0x20000
  242. #define CONFIG_ENV_SIZE 0x2000
  243. #endif
  244. #endif
  245. /* Debug Server firmware */
  246. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  247. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  248. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  249. /*
  250. * I2C
  251. */
  252. #define I2C_MUX_PCA_ADDR 0x77
  253. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  254. /* I2C bus multiplexer */
  255. #define I2C_MUX_CH_DEFAULT 0x8
  256. /* SPI */
  257. #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
  258. #define CONFIG_SPI_FLASH
  259. #ifdef CONFIG_FSL_DSPI
  260. #define CONFIG_SPI_FLASH_STMICRO
  261. #define CONFIG_SPI_FLASH_SST
  262. #define CONFIG_SPI_FLASH_EON
  263. #endif
  264. #ifdef CONFIG_FSL_QSPI
  265. #define CONFIG_SPI_FLASH_SPANSION
  266. #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
  267. #define FSL_QSPI_FLASH_NUM 4
  268. #endif
  269. /*
  270. * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
  271. * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
  272. * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
  273. */
  274. #define FSL_QIXIS_BRDCFG9_QSPI 0x1
  275. #endif
  276. /*
  277. * MMC
  278. */
  279. #ifdef CONFIG_MMC
  280. #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
  281. QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  282. #endif
  283. /*
  284. * RTC configuration
  285. */
  286. #define RTC
  287. #define CONFIG_RTC_DS3231 1
  288. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  289. /* EEPROM */
  290. #define CONFIG_ID_EEPROM
  291. #define CONFIG_SYS_I2C_EEPROM_NXID
  292. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  293. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  294. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  295. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  296. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  297. #define CONFIG_FSL_MEMAC
  298. #ifdef CONFIG_PCI
  299. #define CONFIG_PCI_SCAN_SHOW
  300. #endif
  301. /* MMC */
  302. #ifdef CONFIG_MMC
  303. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  304. #endif
  305. /* Initial environment variables */
  306. #undef CONFIG_EXTRA_ENV_SETTINGS
  307. #ifdef CONFIG_SECURE_BOOT
  308. #define CONFIG_EXTRA_ENV_SETTINGS \
  309. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  310. "loadaddr=0x80100000\0" \
  311. "kernel_addr=0x100000\0" \
  312. "ramdisk_addr=0x800000\0" \
  313. "ramdisk_size=0x2000000\0" \
  314. "fdt_high=0xa0000000\0" \
  315. "initrd_high=0xffffffffffffffff\0" \
  316. "kernel_start=0x581000000\0" \
  317. "kernel_load=0xa0000000\0" \
  318. "kernel_size=0x2800000\0" \
  319. "mcmemsize=0x40000000\0" \
  320. "mcinitcmd=esbc_validate 0x580700000;" \
  321. "esbc_validate 0x580740000;" \
  322. "fsl_mc start mc 0x580a00000" \
  323. " 0x580e00000 \0"
  324. #elif defined(CONFIG_SD_BOOT)
  325. #define CONFIG_EXTRA_ENV_SETTINGS \
  326. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  327. "loadaddr=0x90100000\0" \
  328. "kernel_addr=0x800\0" \
  329. "ramdisk_addr=0x800000\0" \
  330. "ramdisk_size=0x2000000\0" \
  331. "fdt_high=0xa0000000\0" \
  332. "initrd_high=0xffffffffffffffff\0" \
  333. "kernel_start=0x8000\0" \
  334. "kernel_load=0xa0000000\0" \
  335. "kernel_size=0x14000\0" \
  336. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  337. "mmc read 0x80100000 0x7000 0x800;" \
  338. "fsl_mc start mc 0x80000000 0x80100000\0" \
  339. "mcmemsize=0x70000000 \0"
  340. #else
  341. #define CONFIG_EXTRA_ENV_SETTINGS \
  342. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  343. "loadaddr=0x80100000\0" \
  344. "kernel_addr=0x100000\0" \
  345. "ramdisk_addr=0x800000\0" \
  346. "ramdisk_size=0x2000000\0" \
  347. "fdt_high=0xa0000000\0" \
  348. "initrd_high=0xffffffffffffffff\0" \
  349. "kernel_start=0x581000000\0" \
  350. "kernel_load=0xa0000000\0" \
  351. "kernel_size=0x2800000\0" \
  352. "mcmemsize=0x40000000\0" \
  353. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  354. " 0x580e00000 \0"
  355. #endif /* CONFIG_SECURE_BOOT */
  356. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  357. #define CONFIG_FSL_MEMAC
  358. #define CONFIG_PHYLIB_10G
  359. #define CONFIG_PHY_VITESSE
  360. #define CONFIG_PHY_REALTEK
  361. #define CONFIG_PHY_TERANETICS
  362. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  363. #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
  364. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  365. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  366. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  367. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  368. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  369. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  370. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  371. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  372. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  373. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  374. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  375. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  376. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  377. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  378. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  379. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  380. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  381. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  382. #define CONFIG_MII /* MII PHY management */
  383. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  384. #endif
  385. #include <asm/fsl_secure_boot.h>
  386. #endif /* __LS2_QDS_H */