ls1043ardb.h 8.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #ifndef __LS1043ARDB_H__
  6. #define __LS1043ARDB_H__
  7. #include "ls1043a_common.h"
  8. #define CONFIG_SYS_CLK_FREQ 100000000
  9. #define CONFIG_DDR_CLK_FREQ 100000000
  10. #define CONFIG_LAYERSCAPE_NS_ACCESS
  11. #define CONFIG_MISC_INIT_R
  12. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  13. /* Physical Memory Map */
  14. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  15. #define CONFIG_NR_DRAM_BANKS 2
  16. #define CONFIG_SYS_SPD_BUS_NUM 0
  17. #ifndef CONFIG_SPL
  18. #define CONFIG_SYS_DDR_RAW_TIMING
  19. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  20. #define CONFIG_FSL_DDR_BIST
  21. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  22. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  23. #endif
  24. #ifdef CONFIG_RAMBOOT_PBL
  25. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  26. #endif
  27. #ifdef CONFIG_NAND_BOOT
  28. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  29. #endif
  30. #ifdef CONFIG_SD_BOOT
  31. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  32. #define CONFIG_CMD_SPL
  33. #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
  34. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  35. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
  36. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
  37. #endif
  38. /*
  39. * NOR Flash Definitions
  40. */
  41. #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
  42. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  43. #define CONFIG_SYS_NOR_CSPR \
  44. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  45. CSPR_PORT_SIZE_16 | \
  46. CSPR_MSEL_NOR | \
  47. CSPR_V)
  48. /* NOR Flash Timing Params */
  49. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  50. CSOR_NOR_TRHZ_80)
  51. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  52. FTIM0_NOR_TEADC(0x1) | \
  53. FTIM0_NOR_TAVDS(0x0) | \
  54. FTIM0_NOR_TEAHC(0xc))
  55. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
  56. FTIM1_NOR_TRAD_NOR(0xb) | \
  57. FTIM1_NOR_TSEQRAD_NOR(0x9))
  58. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
  59. FTIM2_NOR_TCH(0x4) | \
  60. FTIM2_NOR_TWPH(0x8) | \
  61. FTIM2_NOR_TWP(0x10))
  62. #define CONFIG_SYS_NOR_FTIM3 0
  63. #define CONFIG_SYS_IFC_CCR 0x01000000
  64. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  65. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  66. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  67. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  68. #define CONFIG_SYS_FLASH_EMPTY_INFO
  69. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  70. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  71. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  72. /*
  73. * NAND Flash Definitions
  74. */
  75. #ifndef SPL_NO_IFC
  76. #define CONFIG_NAND_FSL_IFC
  77. #endif
  78. #define CONFIG_SYS_NAND_BASE 0x7e800000
  79. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  80. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  81. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  82. | CSPR_PORT_SIZE_8 \
  83. | CSPR_MSEL_NAND \
  84. | CSPR_V)
  85. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  86. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  87. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  88. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  89. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  90. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  91. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  92. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  93. #define CONFIG_SYS_NAND_ONFI_DETECTION
  94. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  95. FTIM0_NAND_TWP(0x18) | \
  96. FTIM0_NAND_TWCHT(0x7) | \
  97. FTIM0_NAND_TWH(0xa))
  98. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  99. FTIM1_NAND_TWBE(0x39) | \
  100. FTIM1_NAND_TRR(0xe) | \
  101. FTIM1_NAND_TRP(0x18))
  102. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  103. FTIM2_NAND_TREH(0xa) | \
  104. FTIM2_NAND_TWHRE(0x1e))
  105. #define CONFIG_SYS_NAND_FTIM3 0x0
  106. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  107. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  108. #define CONFIG_MTD_NAND_VERIFY_WRITE
  109. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  110. #ifdef CONFIG_NAND_BOOT
  111. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  112. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  113. #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
  114. #endif
  115. /*
  116. * CPLD
  117. */
  118. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  119. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  120. #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
  121. #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  122. CSPR_PORT_SIZE_8 | \
  123. CSPR_MSEL_GPCM | \
  124. CSPR_V)
  125. #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
  126. #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  127. CSOR_NOR_NOR_MODE_AVD_NOR | \
  128. CSOR_NOR_TRHZ_80)
  129. /* CPLD Timing parameters for IFC GPCM */
  130. #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  131. FTIM0_GPCM_TEADC(0xf) | \
  132. FTIM0_GPCM_TEAHC(0xf))
  133. #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  134. FTIM1_GPCM_TRAD(0x3f))
  135. #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  136. FTIM2_GPCM_TCH(0xf) | \
  137. FTIM2_GPCM_TWP(0xff))
  138. #define CONFIG_SYS_CPLD_FTIM3 0x0
  139. /* IFC Timing Params */
  140. #ifdef CONFIG_NAND_BOOT
  141. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  142. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  143. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  144. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  145. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  146. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  147. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  148. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  149. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  150. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  151. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  152. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  153. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  154. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  155. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  156. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  157. #else
  158. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  159. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  160. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  161. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  162. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  163. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  164. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  165. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  166. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  167. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  168. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  169. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  170. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  171. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  172. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  173. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  174. #endif
  175. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
  176. #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
  177. #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
  178. #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
  179. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
  180. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
  181. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
  182. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
  183. /* EEPROM */
  184. #ifndef SPL_NO_EEPROM
  185. #define CONFIG_ID_EEPROM
  186. #define CONFIG_SYS_I2C_EEPROM_NXID
  187. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  188. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  189. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  190. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  191. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  192. #endif
  193. /*
  194. * Environment
  195. */
  196. #ifndef SPL_NO_ENV
  197. #define CONFIG_ENV_OVERWRITE
  198. #endif
  199. #if defined(CONFIG_NAND_BOOT)
  200. #define CONFIG_ENV_SIZE 0x2000
  201. #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
  202. #elif defined(CONFIG_SD_BOOT)
  203. #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
  204. #define CONFIG_SYS_MMC_ENV_DEV 0
  205. #define CONFIG_ENV_SIZE 0x2000
  206. #else
  207. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
  208. #define CONFIG_ENV_SECT_SIZE 0x20000
  209. #define CONFIG_ENV_SIZE 0x20000
  210. #endif
  211. /* FMan */
  212. #ifndef SPL_NO_FMAN
  213. #define AQR105_IRQ_MASK 0x40000000
  214. #ifdef CONFIG_NET
  215. #define CONFIG_PHY_VITESSE
  216. #define CONFIG_PHY_REALTEK
  217. #endif
  218. #ifdef CONFIG_SYS_DPAA_FMAN
  219. #define CONFIG_FMAN_ENET
  220. #define CONFIG_PHYLIB_10G
  221. #define CONFIG_PHY_AQUANTIA
  222. #define RGMII_PHY1_ADDR 0x1
  223. #define RGMII_PHY2_ADDR 0x2
  224. #define QSGMII_PORT1_PHY_ADDR 0x4
  225. #define QSGMII_PORT2_PHY_ADDR 0x5
  226. #define QSGMII_PORT3_PHY_ADDR 0x6
  227. #define QSGMII_PORT4_PHY_ADDR 0x7
  228. #define FM1_10GEC1_PHY_ADDR 0x1
  229. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  230. #endif
  231. #endif
  232. /* QE */
  233. #ifndef SPL_NO_QE
  234. #if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
  235. #define CONFIG_U_QE
  236. #endif
  237. #endif
  238. /* SATA */
  239. #ifndef SPL_NO_SATA
  240. #ifndef CONFIG_CMD_EXT2
  241. #define CONFIG_CMD_EXT2
  242. #endif
  243. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
  244. #define CONFIG_SYS_SCSI_MAX_LUN 2
  245. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  246. CONFIG_SYS_SCSI_MAX_LUN)
  247. #define SCSI_VEND_ID 0x1b4b
  248. #define SCSI_DEV_ID 0x9170
  249. #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
  250. #endif
  251. #include <asm/fsl_secure_boot.h>
  252. #endif /* __LS1043ARDB_H__ */