ls1043a_common.h 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor
  4. */
  5. #ifndef __LS1043A_COMMON_H
  6. #define __LS1043A_COMMON_H
  7. /* SPL build */
  8. #ifdef CONFIG_SPL_BUILD
  9. #define SPL_NO_FMAN
  10. #define SPL_NO_DSPI
  11. #define SPL_NO_PCIE
  12. #define SPL_NO_ENV
  13. #define SPL_NO_MISC
  14. #define SPL_NO_USB
  15. #define SPL_NO_SATA
  16. #define SPL_NO_QE
  17. #define SPL_NO_EEPROM
  18. #endif
  19. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  20. #define SPL_NO_MMC
  21. #endif
  22. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  23. #define SPL_NO_IFC
  24. #endif
  25. #define CONFIG_REMAKE_ELF
  26. #define CONFIG_FSL_LAYERSCAPE
  27. #define CONFIG_MP
  28. #define CONFIG_GICV2
  29. #include <asm/arch/stream_id_lsch2.h>
  30. #include <asm/arch/config.h>
  31. /* Link Definitions */
  32. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  33. #define CONFIG_SKIP_LOWLEVEL_INIT
  34. #define CONFIG_VERY_BIG_RAM
  35. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  36. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  37. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  38. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  39. #define CPU_RELEASE_ADDR secondary_boot_func
  40. /* Generic Timer Definitions */
  41. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  42. /* Size of malloc() pool */
  43. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  44. /* Serial Port */
  45. #define CONFIG_SYS_NS16550_SERIAL
  46. #define CONFIG_SYS_NS16550_REG_SIZE 1
  47. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  48. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  49. /* SD boot SPL */
  50. #ifdef CONFIG_SD_BOOT
  51. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  52. #define CONFIG_SPL_TEXT_BASE 0x10000000
  53. #define CONFIG_SPL_MAX_SIZE 0x17000
  54. #define CONFIG_SPL_STACK 0x1001e000
  55. #define CONFIG_SPL_PAD_TO 0x1d000
  56. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  57. CONFIG_SPL_BSS_MAX_SIZE)
  58. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  59. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  60. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  61. #ifdef CONFIG_SECURE_BOOT
  62. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  63. /*
  64. * HDR would be appended at end of image and copied to DDR along
  65. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  66. * size increases then increase this size in case of secure boot as
  67. * it uses raw u-boot image instead of fit image.
  68. */
  69. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  70. #else
  71. #define CONFIG_SYS_MONITOR_LEN 0x100000
  72. #endif /* ifdef CONFIG_SECURE_BOOT */
  73. #endif
  74. /* NAND SPL */
  75. #ifdef CONFIG_NAND_BOOT
  76. #define CONFIG_SPL_PBL_PAD
  77. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  78. #define CONFIG_SPL_TEXT_BASE 0x10000000
  79. #define CONFIG_SPL_MAX_SIZE 0x1a000
  80. #define CONFIG_SPL_STACK 0x1001d000
  81. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  82. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  83. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  84. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  85. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  86. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  87. #ifdef CONFIG_SECURE_BOOT
  88. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  89. #endif /* ifdef CONFIG_SECURE_BOOT */
  90. #ifdef CONFIG_U_BOOT_HDR_SIZE
  91. /*
  92. * HDR would be appended at end of image and copied to DDR along
  93. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  94. * size increases then increase this size in case of secure boot as
  95. * it uses raw u-boot image instead of fit image.
  96. */
  97. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  98. #else
  99. #define CONFIG_SYS_MONITOR_LEN 0x100000
  100. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  101. #endif
  102. /* IFC */
  103. #ifndef SPL_NO_IFC
  104. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  105. #define CONFIG_FSL_IFC
  106. /*
  107. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  108. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  109. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  110. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  111. */
  112. #define CONFIG_SYS_FLASH_BASE 0x60000000
  113. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  114. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  115. #ifdef CONFIG_MTD_NOR_FLASH
  116. #define CONFIG_FLASH_CFI_DRIVER
  117. #define CONFIG_SYS_FLASH_CFI
  118. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  119. #define CONFIG_SYS_FLASH_QUIET_TEST
  120. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  121. #endif
  122. #endif
  123. #endif
  124. /* I2C */
  125. #define CONFIG_SYS_I2C
  126. /* PCIe */
  127. #ifndef SPL_NO_PCIE
  128. #define CONFIG_PCIE1 /* PCIE controller 1 */
  129. #define CONFIG_PCIE2 /* PCIE controller 2 */
  130. #define CONFIG_PCIE3 /* PCIE controller 3 */
  131. #ifdef CONFIG_PCI
  132. #define CONFIG_PCI_SCAN_SHOW
  133. #endif
  134. #endif
  135. /* Command line configuration */
  136. /* MMC */
  137. #ifndef SPL_NO_MMC
  138. #ifdef CONFIG_MMC
  139. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  140. #endif
  141. #endif
  142. /* DSPI */
  143. #ifndef SPL_NO_DSPI
  144. #define CONFIG_FSL_DSPI
  145. #ifdef CONFIG_FSL_DSPI
  146. #define CONFIG_DM_SPI_FLASH
  147. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  148. #define CONFIG_SPI_FLASH_SST /* cs1 */
  149. #define CONFIG_SPI_FLASH_EON /* cs2 */
  150. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  151. #define CONFIG_SF_DEFAULT_BUS 1
  152. #define CONFIG_SF_DEFAULT_CS 0
  153. #endif
  154. #endif
  155. #endif
  156. /* FMan ucode */
  157. #ifndef SPL_NO_FMAN
  158. #define CONFIG_SYS_DPAA_FMAN
  159. #ifdef CONFIG_SYS_DPAA_FMAN
  160. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  161. #ifdef CONFIG_NAND_BOOT
  162. /* Store Fman ucode at offeset 0x900000(72 blocks). */
  163. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  164. #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
  165. #elif defined(CONFIG_SD_BOOT)
  166. /*
  167. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  168. * about 1MB (2040 blocks), Env is stored after the image, and the env size is
  169. * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  170. */
  171. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  172. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
  173. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
  174. #elif defined(CONFIG_QSPI_BOOT)
  175. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  176. #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
  177. #define CONFIG_ENV_SPI_BUS 0
  178. #define CONFIG_ENV_SPI_CS 0
  179. #define CONFIG_ENV_SPI_MAX_HZ 1000000
  180. #define CONFIG_ENV_SPI_MODE 0x03
  181. #else
  182. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  183. /* FMan fireware Pre-load address */
  184. #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
  185. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  186. #endif
  187. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  188. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  189. #endif
  190. #endif
  191. /* Miscellaneous configurable options */
  192. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  193. #define CONFIG_HWCONFIG
  194. #define HWCONFIG_BUFFER_SIZE 128
  195. #ifndef SPL_NO_MISC
  196. #ifndef CONFIG_SPL_BUILD
  197. #define BOOT_TARGET_DEVICES(func) \
  198. func(MMC, mmc, 0) \
  199. func(USB, usb, 0)
  200. #include <config_distro_bootcmd.h>
  201. #endif
  202. /* Initial environment variables */
  203. #define CONFIG_EXTRA_ENV_SETTINGS \
  204. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  205. "fdt_high=0xffffffffffffffff\0" \
  206. "initrd_high=0xffffffffffffffff\0" \
  207. "fdt_addr=0x64f00000\0" \
  208. "kernel_addr=0x61000000\0" \
  209. "scriptaddr=0x80000000\0" \
  210. "scripthdraddr=0x80080000\0" \
  211. "fdtheader_addr_r=0x80100000\0" \
  212. "kernelheader_addr_r=0x80200000\0" \
  213. "kernel_addr_r=0x81000000\0" \
  214. "fdt_addr_r=0x90000000\0" \
  215. "load_addr=0xa0000000\0" \
  216. "kernelheader_addr=0x60800000\0" \
  217. "kernel_size=0x2800000\0" \
  218. "kernelheader_size=0x40000\0" \
  219. "kernel_addr_sd=0x8000\0" \
  220. "kernel_size_sd=0x14000\0" \
  221. "kernelhdr_addr_sd=0x4000\0" \
  222. "kernelhdr_size_sd=0x10\0" \
  223. "console=ttyS0,115200\0" \
  224. "boot_os=y\0" \
  225. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  226. BOOTENV \
  227. "boot_scripts=ls1043ardb_boot.scr\0" \
  228. "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
  229. "scan_dev_for_boot_part=" \
  230. "part list ${devtype} ${devnum} devplist; " \
  231. "env exists devplist || setenv devplist 1; " \
  232. "for distro_bootpart in ${devplist}; do " \
  233. "if fstype ${devtype} " \
  234. "${devnum}:${distro_bootpart} " \
  235. "bootfstype; then " \
  236. "run scan_dev_for_boot; " \
  237. "fi; " \
  238. "done\0" \
  239. "scan_dev_for_boot=" \
  240. "echo Scanning ${devtype} " \
  241. "${devnum}:${distro_bootpart}...; " \
  242. "for prefix in ${boot_prefixes}; do " \
  243. "run scan_dev_for_scripts; " \
  244. "done;\0" \
  245. "boot_a_script=" \
  246. "load ${devtype} ${devnum}:${distro_bootpart} " \
  247. "${scriptaddr} ${prefix}${script}; " \
  248. "env exists secureboot && load ${devtype} " \
  249. "${devnum}:${distro_bootpart} " \
  250. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  251. "&& esbc_validate ${scripthdraddr};" \
  252. "source ${scriptaddr}\0" \
  253. "qspi_bootcmd=echo Trying load from qspi..;" \
  254. "sf probe && sf read $load_addr " \
  255. "$kernel_addr $kernel_size; env exists secureboot " \
  256. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  257. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  258. "bootm $load_addr#$board\0" \
  259. "nor_bootcmd=echo Trying load from nor..;" \
  260. "cp.b $kernel_addr $load_addr " \
  261. "$kernel_size; env exists secureboot " \
  262. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  263. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  264. "bootm $load_addr#$board\0" \
  265. "sd_bootcmd=echo Trying load from SD ..;" \
  266. "mmcinfo; mmc read $load_addr " \
  267. "$kernel_addr_sd $kernel_size_sd && " \
  268. "env exists secureboot && mmc read $kernelheader_addr_r " \
  269. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  270. " && esbc_validate ${kernelheader_addr_r};" \
  271. "bootm $load_addr#$board\0"
  272. #undef CONFIG_BOOTCOMMAND
  273. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  274. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  275. "env exists secureboot && esbc_halt;"
  276. #elif defined(CONFIG_SD_BOOT)
  277. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  278. "env exists secureboot && esbc_halt;"
  279. #else
  280. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  281. "env exists secureboot && esbc_halt;"
  282. #endif
  283. #endif
  284. /* Monitor Command Prompt */
  285. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  286. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  287. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  288. #include <asm/arch/soc.h>
  289. #endif /* __LS1043A_COMMON_H */