ls1021aqds.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #define CONFIG_ARMV7_PSCI_1_0
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_FSL_CLK
  10. #define CONFIG_SKIP_LOWLEVEL_INIT
  11. #define CONFIG_DEEP_SLEEP
  12. /*
  13. * Size of malloc() pool
  14. */
  15. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  16. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  17. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  18. #ifndef __ASSEMBLY__
  19. unsigned long get_board_sys_clk(void);
  20. unsigned long get_board_ddr_clk(void);
  21. #endif
  22. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  23. #define CONFIG_SYS_CLK_FREQ 100000000
  24. #define CONFIG_DDR_CLK_FREQ 100000000
  25. #define CONFIG_QIXIS_I2C_ACCESS
  26. #else
  27. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  28. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  29. #endif
  30. #ifdef CONFIG_RAMBOOT_PBL
  31. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
  32. #endif
  33. #ifdef CONFIG_SD_BOOT
  34. #ifdef CONFIG_SD_BOOT_QSPI
  35. #define CONFIG_SYS_FSL_PBL_RCW \
  36. board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  37. #else
  38. #define CONFIG_SYS_FSL_PBL_RCW \
  39. board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  40. #endif
  41. #define CONFIG_SPL_TEXT_BASE 0x10000000
  42. #define CONFIG_SPL_MAX_SIZE 0x1a000
  43. #define CONFIG_SPL_STACK 0x1001d000
  44. #define CONFIG_SPL_PAD_TO 0x1c000
  45. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  46. CONFIG_SYS_MONITOR_LEN)
  47. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  48. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  49. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  50. #define CONFIG_SYS_MONITOR_LEN 0xc0000
  51. #endif
  52. #ifdef CONFIG_NAND_BOOT
  53. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  54. #define CONFIG_SPL_TEXT_BASE 0x10000000
  55. #define CONFIG_SPL_MAX_SIZE 0x1a000
  56. #define CONFIG_SPL_STACK 0x1001d000
  57. #define CONFIG_SPL_PAD_TO 0x1c000
  58. #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
  59. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  60. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  61. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  62. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  63. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  64. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  65. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  66. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  67. #define CONFIG_SYS_MONITOR_LEN 0x80000
  68. #endif
  69. #define CONFIG_NR_DRAM_BANKS 1
  70. #define CONFIG_DDR_SPD
  71. #define SPD_EEPROM_ADDRESS 0x51
  72. #define CONFIG_SYS_SPD_BUS_NUM 0
  73. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  74. #ifndef CONFIG_SYS_FSL_DDR4
  75. #define CONFIG_SYS_DDR_RAW_TIMING
  76. #endif
  77. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  78. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  79. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  80. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  81. #define CONFIG_DDR_ECC
  82. #ifdef CONFIG_DDR_ECC
  83. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  84. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  85. #endif
  86. #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
  87. !defined(CONFIG_QSPI_BOOT)
  88. #define CONFIG_U_QE
  89. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  90. #endif
  91. /*
  92. * IFC Definitions
  93. */
  94. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  95. #define CONFIG_FSL_IFC
  96. #define CONFIG_SYS_FLASH_BASE 0x60000000
  97. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  98. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  99. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  100. CSPR_PORT_SIZE_16 | \
  101. CSPR_MSEL_NOR | \
  102. CSPR_V)
  103. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  104. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  105. + 0x8000000) | \
  106. CSPR_PORT_SIZE_16 | \
  107. CSPR_MSEL_NOR | \
  108. CSPR_V)
  109. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  110. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  111. CSOR_NOR_TRHZ_80)
  112. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  113. FTIM0_NOR_TEADC(0x5) | \
  114. FTIM0_NOR_TEAHC(0x5))
  115. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  116. FTIM1_NOR_TRAD_NOR(0x1a) | \
  117. FTIM1_NOR_TSEQRAD_NOR(0x13))
  118. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  119. FTIM2_NOR_TCH(0x4) | \
  120. FTIM2_NOR_TWPH(0xe) | \
  121. FTIM2_NOR_TWP(0x1c))
  122. #define CONFIG_SYS_NOR_FTIM3 0
  123. #define CONFIG_FLASH_CFI_DRIVER
  124. #define CONFIG_SYS_FLASH_CFI
  125. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  126. #define CONFIG_SYS_FLASH_QUIET_TEST
  127. #define CONFIG_FLASH_SHOW_PROGRESS 45
  128. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  129. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  130. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  132. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  133. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  134. #define CONFIG_SYS_FLASH_EMPTY_INFO
  135. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  136. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  137. /*
  138. * NAND Flash Definitions
  139. */
  140. #define CONFIG_NAND_FSL_IFC
  141. #define CONFIG_SYS_NAND_BASE 0x7e800000
  142. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  143. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  144. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  145. | CSPR_PORT_SIZE_8 \
  146. | CSPR_MSEL_NAND \
  147. | CSPR_V)
  148. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  149. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  150. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  151. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  152. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  153. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  154. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  155. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  156. #define CONFIG_SYS_NAND_ONFI_DETECTION
  157. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  158. FTIM0_NAND_TWP(0x18) | \
  159. FTIM0_NAND_TWCHT(0x7) | \
  160. FTIM0_NAND_TWH(0xa))
  161. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  162. FTIM1_NAND_TWBE(0x39) | \
  163. FTIM1_NAND_TRR(0xe) | \
  164. FTIM1_NAND_TRP(0x18))
  165. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  166. FTIM2_NAND_TREH(0xa) | \
  167. FTIM2_NAND_TWHRE(0x1e))
  168. #define CONFIG_SYS_NAND_FTIM3 0x0
  169. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  170. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  171. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  172. #endif
  173. /*
  174. * QIXIS Definitions
  175. */
  176. #define CONFIG_FSL_QIXIS
  177. #ifdef CONFIG_FSL_QIXIS
  178. #define QIXIS_BASE 0x7fb00000
  179. #define QIXIS_BASE_PHYS QIXIS_BASE
  180. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  181. #define QIXIS_LBMAP_SWITCH 6
  182. #define QIXIS_LBMAP_MASK 0x0f
  183. #define QIXIS_LBMAP_SHIFT 0
  184. #define QIXIS_LBMAP_DFLTBANK 0x00
  185. #define QIXIS_LBMAP_ALTBANK 0x04
  186. #define QIXIS_PWR_CTL 0x21
  187. #define QIXIS_PWR_CTL_POWEROFF 0x80
  188. #define QIXIS_RST_CTL_RESET 0x44
  189. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  190. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  191. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  192. #define QIXIS_CTL_SYS 0x5
  193. #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
  194. #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
  195. #define QIXIS_RST_FORCE_3 0x45
  196. #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
  197. #define QIXIS_PWR_CTL2 0x21
  198. #define QIXIS_PWR_CTL2_PCTL 0x2
  199. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  200. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  201. CSPR_PORT_SIZE_8 | \
  202. CSPR_MSEL_GPCM | \
  203. CSPR_V)
  204. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  205. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  206. CSOR_NOR_NOR_MODE_AVD_NOR | \
  207. CSOR_NOR_TRHZ_80)
  208. /*
  209. * QIXIS Timing parameters for IFC GPCM
  210. */
  211. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
  212. FTIM0_GPCM_TEADC(0xe) | \
  213. FTIM0_GPCM_TEAHC(0xe))
  214. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
  215. FTIM1_GPCM_TRAD(0x1f))
  216. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
  217. FTIM2_GPCM_TCH(0xe) | \
  218. FTIM2_GPCM_TWP(0xf0))
  219. #define CONFIG_SYS_FPGA_FTIM3 0x0
  220. #endif
  221. #if defined(CONFIG_NAND_BOOT)
  222. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  223. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  224. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  225. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  226. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  227. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  228. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  229. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  230. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  231. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  232. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  233. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  234. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  235. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  236. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  237. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  238. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  239. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  240. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  241. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  242. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  243. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  244. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  245. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  246. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  247. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  248. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  249. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  250. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  251. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  252. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  253. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  254. #else
  255. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  256. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  257. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  258. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  259. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  260. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  261. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  262. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  263. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  264. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  265. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  266. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  267. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  268. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  269. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  270. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  271. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  272. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  273. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  274. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  275. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  276. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  277. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  278. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  279. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  280. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  281. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  282. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  283. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  284. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  285. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  286. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  287. #endif
  288. /*
  289. * Serial Port
  290. */
  291. #ifdef CONFIG_LPUART
  292. #define CONFIG_LPUART_32B_REG
  293. #else
  294. #define CONFIG_SYS_NS16550_SERIAL
  295. #ifndef CONFIG_DM_SERIAL
  296. #define CONFIG_SYS_NS16550_REG_SIZE 1
  297. #endif
  298. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  299. #endif
  300. /*
  301. * I2C
  302. */
  303. #define CONFIG_SYS_I2C
  304. #define CONFIG_SYS_I2C_MXC
  305. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  306. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  307. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  308. /*
  309. * I2C bus multiplexer
  310. */
  311. #define I2C_MUX_PCA_ADDR_PRI 0x77
  312. #define I2C_MUX_CH_DEFAULT 0x8
  313. #define I2C_MUX_CH_CH7301 0xC
  314. /*
  315. * MMC
  316. */
  317. /* SPI */
  318. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  319. /* QSPI */
  320. #define QSPI0_AMBA_BASE 0x40000000
  321. #define FSL_QSPI_FLASH_SIZE (1 << 24)
  322. #define FSL_QSPI_FLASH_NUM 2
  323. /* DSPI */
  324. /* DM SPI */
  325. #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
  326. #define CONFIG_DM_SPI_FLASH
  327. #define CONFIG_SPI_FLASH_DATAFLASH
  328. #endif
  329. #endif
  330. /*
  331. * Video
  332. */
  333. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  334. #define CONFIG_VIDEO_LOGO
  335. #define CONFIG_VIDEO_BMP_LOGO
  336. #define CONFIG_FSL_DIU_CH7301
  337. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  338. #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
  339. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  340. #endif
  341. /*
  342. * eTSEC
  343. */
  344. #ifdef CONFIG_TSEC_ENET
  345. #define CONFIG_MII
  346. #define CONFIG_MII_DEFAULT_TSEC 3
  347. #define CONFIG_TSEC1 1
  348. #define CONFIG_TSEC1_NAME "eTSEC1"
  349. #define CONFIG_TSEC2 1
  350. #define CONFIG_TSEC2_NAME "eTSEC2"
  351. #define CONFIG_TSEC3 1
  352. #define CONFIG_TSEC3_NAME "eTSEC3"
  353. #define TSEC1_PHY_ADDR 1
  354. #define TSEC2_PHY_ADDR 2
  355. #define TSEC3_PHY_ADDR 3
  356. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  357. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  358. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  359. #define TSEC1_PHYIDX 0
  360. #define TSEC2_PHYIDX 0
  361. #define TSEC3_PHYIDX 0
  362. #define CONFIG_ETHPRIME "eTSEC1"
  363. #define CONFIG_PHY_REALTEK
  364. #define CONFIG_HAS_ETH0
  365. #define CONFIG_HAS_ETH1
  366. #define CONFIG_HAS_ETH2
  367. #define CONFIG_FSL_SGMII_RISER 1
  368. #define SGMII_RISER_PHY_OFFSET 0x1b
  369. #ifdef CONFIG_FSL_SGMII_RISER
  370. #define CONFIG_SYS_TBIPA_VALUE 8
  371. #endif
  372. #endif
  373. /* PCIe */
  374. #define CONFIG_PCIE1 /* PCIE controller 1 */
  375. #define CONFIG_PCIE2 /* PCIE controller 2 */
  376. #ifdef CONFIG_PCI
  377. #define CONFIG_PCI_SCAN_SHOW
  378. #endif
  379. #define CONFIG_CMDLINE_TAG
  380. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  381. #define CONFIG_LAYERSCAPE_NS_ACCESS
  382. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  383. #define COUNTER_FREQUENCY 12500000
  384. #define CONFIG_HWCONFIG
  385. #define HWCONFIG_BUFFER_SIZE 256
  386. #define CONFIG_FSL_DEVICE_DISABLE
  387. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  388. #ifdef CONFIG_LPUART
  389. #define CONFIG_EXTRA_ENV_SETTINGS \
  390. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
  391. "fdt_high=0xffffffff\0" \
  392. "initrd_high=0xffffffff\0" \
  393. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  394. #else
  395. #define CONFIG_EXTRA_ENV_SETTINGS \
  396. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  397. "fdt_high=0xffffffff\0" \
  398. "initrd_high=0xffffffff\0" \
  399. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  400. #endif
  401. /*
  402. * Miscellaneous configurable options
  403. */
  404. #define CONFIG_SYS_MEMTEST_START 0x80000000
  405. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  406. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  407. #define CONFIG_LS102XA_STREAM_ID
  408. #define CONFIG_SYS_INIT_SP_OFFSET \
  409. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  410. #define CONFIG_SYS_INIT_SP_ADDR \
  411. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  412. #ifdef CONFIG_SPL_BUILD
  413. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  414. #else
  415. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  416. #endif
  417. /*
  418. * Environment
  419. */
  420. #define CONFIG_ENV_OVERWRITE
  421. #if defined(CONFIG_SD_BOOT)
  422. #define CONFIG_ENV_OFFSET 0x300000
  423. #define CONFIG_SYS_MMC_ENV_DEV 0
  424. #define CONFIG_ENV_SIZE 0x2000
  425. #elif defined(CONFIG_QSPI_BOOT)
  426. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  427. #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
  428. #define CONFIG_ENV_SECT_SIZE 0x10000
  429. #elif defined(CONFIG_NAND_BOOT)
  430. #define CONFIG_ENV_SIZE 0x2000
  431. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  432. #else
  433. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
  434. #define CONFIG_ENV_SIZE 0x2000
  435. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  436. #endif
  437. #define CONFIG_MISC_INIT_R
  438. #include <asm/fsl_secure_boot.h>
  439. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  440. #endif