ls1012aqds.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1012AQDS_H__
  6. #define __LS1012AQDS_H__
  7. #include "ls1012a_common.h"
  8. /* DDR */
  9. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  10. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  11. #define CONFIG_NR_DRAM_BANKS 2
  12. #define CONFIG_SYS_SDRAM_SIZE 0x40000000
  13. #define CONFIG_CMD_MEMINFO
  14. #define CONFIG_SYS_MEMTEST_START 0x80000000
  15. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  16. /*
  17. * QIXIS Definitions
  18. */
  19. #define CONFIG_FSL_QIXIS
  20. #ifdef CONFIG_FSL_QIXIS
  21. #define CONFIG_QIXIS_I2C_ACCESS
  22. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  23. #define QIXIS_LBMAP_BRDCFG_REG 0x04
  24. #define QIXIS_LBMAP_SWITCH 6
  25. #define QIXIS_LBMAP_MASK 0x08
  26. #define QIXIS_LBMAP_SHIFT 0
  27. #define QIXIS_LBMAP_DFLTBANK 0x00
  28. #define QIXIS_LBMAP_ALTBANK 0x08
  29. #define QIXIS_RST_CTL_RESET 0x31
  30. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  31. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  32. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  33. #endif
  34. /*
  35. * I2C bus multiplexer
  36. */
  37. #define I2C_MUX_PCA_ADDR_PRI 0x77
  38. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  39. #define I2C_RETIMER_ADDR 0x18
  40. #define I2C_MUX_CH_DEFAULT 0x8
  41. #define I2C_MUX_CH_CH7301 0xC
  42. #define I2C_MUX_CH5 0xD
  43. #define I2C_MUX_CH7 0xF
  44. #define I2C_MUX_CH_VOL_MONITOR 0xa
  45. /*
  46. * RTC configuration
  47. */
  48. #define RTC
  49. #define CONFIG_RTC_PCF8563 1
  50. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  51. /* EEPROM */
  52. #define CONFIG_ID_EEPROM
  53. #define CONFIG_SYS_I2C_EEPROM_NXID
  54. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  55. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  56. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  57. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  58. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  59. /* Voltage monitor on channel 2*/
  60. #define I2C_VOL_MONITOR_ADDR 0x40
  61. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  62. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  63. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  64. /* DSPI */
  65. #define CONFIG_FSL_DSPI1
  66. #define CONFIG_DEFAULT_SPI_BUS 1
  67. #define CONFIG_CMD_SPI
  68. #define MMAP_DSPI DSPI1_BASE_ADDR
  69. #define CONFIG_SYS_DSPI_CTAR0 1
  70. #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  71. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  72. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  73. DSPI_CTAR_DT(0))
  74. #define CONFIG_SPI_FLASH_SST /* cs1 */
  75. #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  76. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  77. DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
  78. DSPI_CTAR_DT(0))
  79. #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
  80. #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  81. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  82. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  83. DSPI_CTAR_DT(0))
  84. #define CONFIG_SPI_FLASH_EON /* cs3 */
  85. #define CONFIG_SF_DEFAULT_SPEED 10000000
  86. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  87. #define CONFIG_SF_DEFAULT_BUS 1
  88. #define CONFIG_SF_DEFAULT_CS 0
  89. /* MMC */
  90. #ifdef CONFIG_MMC
  91. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  92. #endif
  93. #define CONFIG_PCIE1 /* PCIE controller 1 */
  94. #define CONFIG_PCI_SCAN_SHOW
  95. #define CONFIG_CMD_MEMINFO
  96. #define CONFIG_SYS_MEMTEST_START 0x80000000
  97. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  98. #define CONFIG_MISC_INIT_R
  99. #endif /* __LS1012AQDS_H__ */