km8360.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2012
  4. * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
  5. * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /* KMBEC FPGA (PRIO) */
  10. #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
  11. #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
  12. #if defined CONFIG_KMETER1
  13. #define CONFIG_HOSTNAME "kmeter1"
  14. #define CONFIG_KM_BOARD_NAME "kmeter1"
  15. #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
  16. #elif defined CONFIG_KMCOGE5NE
  17. #define CONFIG_HOSTNAME "kmcoge5ne"
  18. #define CONFIG_KM_BOARD_NAME "kmcoge5ne"
  19. #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
  20. #define CONFIG_NAND_ECC_BCH
  21. #define CONFIG_NAND_KMETER1
  22. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  23. #define NAND_MAX_CHIPS 1
  24. #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
  25. #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
  26. #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
  27. #else
  28. #error ("Board not supported")
  29. #endif
  30. /*
  31. * High Level Configuration Options
  32. */
  33. #define CONFIG_QE /* Has QE */
  34. #define CONFIG_MPC8360 /* MPC8360 CPU specific */
  35. /* include common defines/options for all 83xx Keymile boards */
  36. #include "km/km83xx-common.h"
  37. /*
  38. * System IO Setup
  39. */
  40. #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  41. /*
  42. * Hardware Reset Configuration Word
  43. */
  44. #define CONFIG_SYS_HRCW_LOW (\
  45. HRCWL_CSB_TO_CLKIN_4X1 | \
  46. HRCWL_CORE_TO_CSB_2X1 | \
  47. HRCWL_CE_PLL_VCO_DIV_2 | \
  48. HRCWL_CE_TO_PLL_1X6)
  49. #define CONFIG_SYS_HRCW_HIGH (\
  50. HRCWH_CORE_ENABLE | \
  51. HRCWH_FROM_0X00000100 | \
  52. HRCWH_BOOTSEQ_DISABLE | \
  53. HRCWH_SW_WATCHDOG_DISABLE | \
  54. HRCWH_ROM_LOC_LOCAL_16BIT | \
  55. HRCWH_BIG_ENDIAN | \
  56. HRCWH_LALE_EARLY | \
  57. HRCWH_LDP_CLEAR)
  58. /**
  59. * DDR RAM settings
  60. */
  61. #define CONFIG_SYS_DDR_SDRAM_CFG (\
  62. SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  63. SDRAM_CFG_SREN | \
  64. SDRAM_CFG_HSE)
  65. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  66. #ifdef CONFIG_KMCOGE5NE
  67. /**
  68. * KMCOGE5NE has 512 MB RAM
  69. */
  70. #define CONFIG_SYS_DDR_CS0_CONFIG (\
  71. CSCONFIG_EN | \
  72. CSCONFIG_AP | \
  73. CSCONFIG_ODT_WR_ONLY_CURRENT | \
  74. CSCONFIG_BANK_BIT_3 | \
  75. CSCONFIG_ROW_BIT_13 | \
  76. CSCONFIG_COL_BIT_10)
  77. #else
  78. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
  79. CSCONFIG_ROW_BIT_13 | \
  80. CSCONFIG_COL_BIT_10 | \
  81. CSCONFIG_ODT_WR_ONLY_CURRENT)
  82. #endif
  83. #define CONFIG_SYS_DDR_CLK_CNTL (\
  84. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  85. #define CONFIG_SYS_DDR_INTERVAL (\
  86. (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  87. (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  88. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
  89. #define CONFIG_SYS_DDRCDR (\
  90. DDRCDR_EN | \
  91. DDRCDR_Q_DRN)
  92. #define CONFIG_SYS_DDR_MODE 0x47860452
  93. #define CONFIG_SYS_DDR_MODE2 0x8080c000
  94. #define CONFIG_SYS_DDR_TIMING_0 (\
  95. (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  96. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  97. (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  98. (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  99. (0 << TIMING_CFG0_WWT_SHIFT) | \
  100. (0 << TIMING_CFG0_RRT_SHIFT) | \
  101. (0 << TIMING_CFG0_WRT_SHIFT) | \
  102. (0 << TIMING_CFG0_RWT_SHIFT))
  103. #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  104. (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  105. (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  106. (3 << TIMING_CFG1_WRREC_SHIFT) | \
  107. (7 << TIMING_CFG1_REFREC_SHIFT) | \
  108. (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  109. (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  110. (3 << TIMING_CFG1_PRETOACT_SHIFT))
  111. #define CONFIG_SYS_DDR_TIMING_2 (\
  112. (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  113. (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  114. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  115. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  116. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  117. (5 << TIMING_CFG2_CPO_SHIFT) | \
  118. (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  119. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  120. /* EEprom support */
  121. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  122. /*
  123. * Local Bus Configuration & Clock Setup
  124. */
  125. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  126. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
  127. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  128. /*
  129. * PAXE on the local bus CS3
  130. */
  131. #define CONFIG_SYS_PAXE_BASE 0xA0000000
  132. #define CONFIG_SYS_PAXE_SIZE 256
  133. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
  134. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
  135. #define CONFIG_SYS_BR3_PRELIM (\
  136. CONFIG_SYS_PAXE_BASE | \
  137. (1 << BR_PS_SHIFT) | \
  138. BR_V)
  139. #define CONFIG_SYS_OR3_PRELIM (\
  140. MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
  141. OR_GPCM_CSNT | \
  142. OR_GPCM_ACS_DIV2 | \
  143. OR_GPCM_SCY_2 | \
  144. OR_GPCM_TRLX | \
  145. OR_GPCM_EAD)
  146. #ifdef CONFIG_KMCOGE5NE
  147. /*
  148. * BFTIC3 on the local bus CS4
  149. */
  150. #define CONFIG_SYS_BFTIC3_BASE 0xB0000000
  151. #define CONFIG_SYS_BFTIC3_SIZE 256
  152. #define CONFIG_SYS_BR4_PRELIM (\
  153. CONFIG_SYS_BFTIC3_BASE |\
  154. (1 << BR_PS_SHIFT) | \
  155. BR_V)
  156. #define CONFIG_SYS_OR4_PRELIM (\
  157. MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
  158. OR_GPCM_CSNT | \
  159. OR_GPCM_ACS_DIV2 |\
  160. OR_GPCM_SCY_2 |\
  161. OR_GPCM_TRLX |\
  162. OR_GPCM_EAD)
  163. #endif
  164. /*
  165. * MMU Setup
  166. */
  167. /* PAXE: icache cacheable, but dcache-inhibit and guarded */
  168. #define CONFIG_SYS_IBAT5L (\
  169. CONFIG_SYS_PAXE_BASE | \
  170. BATL_PP_10 | \
  171. BATL_MEMCOHERENCE)
  172. #define CONFIG_SYS_IBAT5U (\
  173. CONFIG_SYS_PAXE_BASE | \
  174. BATU_BL_256M | \
  175. BATU_VS | \
  176. BATU_VP)
  177. #define CONFIG_SYS_DBAT5L (\
  178. CONFIG_SYS_PAXE_BASE | \
  179. BATL_PP_10 | \
  180. BATL_CACHEINHIBIT | \
  181. BATL_GUARDEDSTORAGE)
  182. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  183. #ifdef CONFIG_KMCOGE5NE
  184. /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
  185. #define CONFIG_SYS_IBAT6L (\
  186. CONFIG_SYS_BFTIC3_BASE | \
  187. BATL_PP_10 | \
  188. BATL_MEMCOHERENCE)
  189. #define CONFIG_SYS_IBAT6U (\
  190. CONFIG_SYS_BFTIC3_BASE | \
  191. BATU_BL_256M | \
  192. BATU_VS | \
  193. BATU_VP)
  194. #define CONFIG_SYS_DBAT6L (\
  195. CONFIG_SYS_BFTIC3_BASE | \
  196. BATL_PP_10 | \
  197. BATL_CACHEINHIBIT | \
  198. BATL_GUARDEDSTORAGE)
  199. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  200. /* DDR/LBC SDRAM next 256M: cacheable */
  201. #define CONFIG_SYS_IBAT7L (\
  202. CONFIG_SYS_SDRAM_BASE2 |\
  203. BATL_PP_10 |\
  204. BATL_CACHEINHIBIT |\
  205. BATL_GUARDEDSTORAGE)
  206. #define CONFIG_SYS_IBAT7U (\
  207. CONFIG_SYS_SDRAM_BASE2 |\
  208. BATU_BL_256M |\
  209. BATU_VS |\
  210. BATU_VP)
  211. /* enable POST tests */
  212. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
  213. #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
  214. #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
  215. #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
  216. #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
  217. #else
  218. #define CONFIG_SYS_IBAT6L (0)
  219. #define CONFIG_SYS_IBAT6U (0)
  220. #define CONFIG_SYS_IBAT7L (0)
  221. #define CONFIG_SYS_IBAT7U (0)
  222. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  223. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  224. #endif
  225. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  226. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  227. #endif /* CONFIG */