ids8313.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (c) 2011 IDS GmbH, Germany
  8. * Sergej Stepanov <ste@ids.de>
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_MPC831x
  16. #define CONFIG_MPC8313
  17. #define CONFIG_FSL_ELBC
  18. #define CONFIG_MISC_INIT_R
  19. #define CONFIG_BOOT_RETRY_TIME 900
  20. #define CONFIG_BOOT_RETRY_MIN 30
  21. #define CONFIG_RESET_TO_RETRY
  22. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  23. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  24. #define CONFIG_SYS_IMMR 0xF0000000
  25. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  26. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  27. /*
  28. * Hardware Reset Configuration Word
  29. * if CLKIN is 66.000MHz, then
  30. * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  31. */
  32. #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  33. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  34. HRCWL_CSB_TO_CLKIN_2X1 |\
  35. HRCWL_CORE_TO_CSB_2X1)
  36. #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
  37. HRCWH_CORE_ENABLE |\
  38. HRCWH_FROM_0XFFF00100 |\
  39. HRCWH_BOOTSEQ_DISABLE |\
  40. HRCWH_SW_WATCHDOG_DISABLE |\
  41. HRCWH_ROM_LOC_LOCAL_8BIT |\
  42. HRCWH_RL_EXT_LEGACY |\
  43. HRCWH_TSEC1M_IN_MII |\
  44. HRCWH_TSEC2M_IN_MII |\
  45. HRCWH_BIG_ENDIAN)
  46. #define CONFIG_SYS_SICRH 0x00000000
  47. #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
  48. #define CONFIG_HWCONFIG
  49. #define CONFIG_SYS_HID0_INIT 0x000000000
  50. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
  51. HID0_ENABLE_INSTRUCTION_CACHE |\
  52. HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  53. #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  54. /*
  55. * Definitions for initial stack pointer and data area (in DCACHE )
  56. */
  57. #define CONFIG_SYS_INIT_RAM_LOCK
  58. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  59. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
  60. #define CONFIG_SYS_GBL_DATA_SIZE 0x100
  61. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  62. - CONFIG_SYS_GBL_DATA_SIZE)
  63. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  64. /*
  65. * Local Bus LCRR and LBCR regs
  66. */
  67. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  68. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  69. #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
  70. (0xFF << LBCR_BMT_SHIFT) |\
  71. 0xF)
  72. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  73. /*
  74. * Internal Definitions
  75. */
  76. /*
  77. * DDR Setup
  78. */
  79. #define CONFIG_SYS_DDR_BASE 0x00000000
  80. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  81. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  82. /*
  83. * Manually set up DDR parameters,
  84. * as this board has not the SPD connected to I2C.
  85. */
  86. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  87. #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
  88. 0x00010000 |\
  89. CSCONFIG_ROW_BIT_13 |\
  90. CSCONFIG_COL_BIT_10)
  91. #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
  92. CSCONFIG_BANK_BIT_3)
  93. #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
  94. #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  95. (3 << TIMING_CFG0_WRT_SHIFT) |\
  96. (3 << TIMING_CFG0_RRT_SHIFT) |\
  97. (3 << TIMING_CFG0_WWT_SHIFT) |\
  98. (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  99. (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  100. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  101. (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  102. #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  103. (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  104. (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  105. (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  106. (4 << TIMING_CFG1_REFREC_SHIFT) |\
  107. (4 << TIMING_CFG1_WRREC_SHIFT) |\
  108. (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
  109. (2 << TIMING_CFG1_WRTORD_SHIFT))
  110. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
  111. (5 << TIMING_CFG2_CPO_SHIFT) |\
  112. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
  113. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
  114. (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
  115. (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
  116. (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  117. #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
  118. (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  119. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
  120. SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
  121. SDRAM_CFG_DBW_32 |\
  122. SDRAM_CFG_SDRAM_TYPE_DDR2)
  123. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  124. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
  125. (0x0242 << SDRAM_MODE_SD_SHIFT))
  126. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  127. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
  128. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
  129. DDRCDR_PZ_NOMZ |\
  130. DDRCDR_NZ_NOMZ |\
  131. DDRCDR_ODT |\
  132. DDRCDR_M_ODR |\
  133. DDRCDR_Q_DRN)
  134. /*
  135. * on-board devices
  136. */
  137. #define CONFIG_TSEC1
  138. #define CONFIG_TSEC2
  139. #define CONFIG_HARD_SPI
  140. /*
  141. * NOR FLASH setup
  142. */
  143. #define CONFIG_SYS_FLASH_CFI
  144. #define CONFIG_FLASH_CFI_DRIVER
  145. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  146. #define CONFIG_FLASH_SHOW_PROGRESS 50
  147. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  148. #define CONFIG_SYS_FLASH_BASE 0xFF800000
  149. #define CONFIG_SYS_FLASH_SIZE 8
  150. #define CONFIG_SYS_FLASH_PROTECTION
  151. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  152. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
  153. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  154. BR_PS_8 |\
  155. BR_MS_GPCM |\
  156. BR_V)
  157. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  158. OR_GPCM_SCY_10 |\
  159. OR_GPCM_EHTR |\
  160. OR_GPCM_TRLX |\
  161. OR_GPCM_CSNT |\
  162. OR_GPCM_EAD)
  163. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  164. #define CONFIG_SYS_MAX_FLASH_SECT 128
  165. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
  166. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  167. /*
  168. * NAND FLASH setup
  169. */
  170. #define CONFIG_SYS_NAND_BASE 0xE1000000
  171. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  172. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  173. #define CONFIG_NAND_FSL_ELBC
  174. #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
  175. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  176. #define NAND_CACHE_PAGES 64
  177. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  178. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
  179. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  180. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  181. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
  182. (2<<BR_DECC_SHIFT) |\
  183. BR_PS_8 |\
  184. BR_MS_FCM |\
  185. BR_V)
  186. #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
  187. OR_FCM_PGS |\
  188. OR_FCM_CSCT |\
  189. OR_FCM_CST |\
  190. OR_FCM_CHT |\
  191. OR_FCM_SCY_4 |\
  192. OR_FCM_TRLX |\
  193. OR_FCM_EHTR |\
  194. OR_FCM_RST)
  195. /*
  196. * MRAM setup
  197. */
  198. #define CONFIG_SYS_MRAM_BASE 0xE2000000
  199. #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
  200. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
  201. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
  202. #define CONFIG_SYS_OR_TIMING_MRAM
  203. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
  204. BR_PS_8 |\
  205. BR_MS_GPCM |\
  206. BR_V)
  207. #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
  208. /*
  209. * CPLD setup
  210. */
  211. #define CONFIG_SYS_CPLD_BASE 0xE3000000
  212. #define CONFIG_SYS_CPLD_SIZE 0x8000
  213. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
  214. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
  215. #define CONFIG_SYS_OR_TIMING_MRAM
  216. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
  217. BR_PS_8 |\
  218. BR_MS_GPCM |\
  219. BR_V)
  220. #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
  221. /*
  222. * HW-Watchdog
  223. */
  224. #define CONFIG_WATCHDOG 1
  225. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  226. /*
  227. * I2C setup
  228. */
  229. #define CONFIG_SYS_I2C
  230. #define CONFIG_SYS_I2C_FSL
  231. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  232. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  233. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  234. #define CONFIG_RTC_PCF8563
  235. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  236. /*
  237. * SPI setup
  238. */
  239. #ifdef CONFIG_HARD_SPI
  240. #define CONFIG_SYS_GPIO1_PRELIM
  241. #define CONFIG_SYS_GPIO1_DIR 0x00000001
  242. #define CONFIG_SYS_GPIO1_DAT 0x00000001
  243. #endif
  244. /*
  245. * Ethernet setup
  246. */
  247. #ifdef CONFIG_TSEC1
  248. #define CONFIG_HAS_ETH0
  249. #define CONFIG_TSEC1_NAME "TSEC0"
  250. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  251. #define TSEC1_PHY_ADDR 0x1
  252. #define TSEC1_FLAGS TSEC_GIGABIT
  253. #define TSEC1_PHYIDX 0
  254. #endif
  255. #ifdef CONFIG_TSEC2
  256. #define CONFIG_HAS_ETH1
  257. #define CONFIG_TSEC2_NAME "TSEC1"
  258. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  259. #define TSEC2_PHY_ADDR 0x3
  260. #define TSEC2_FLAGS TSEC_GIGABIT
  261. #define TSEC2_PHYIDX 0
  262. #endif
  263. #define CONFIG_ETHPRIME "TSEC1"
  264. /*
  265. * Serial Port
  266. */
  267. #define CONFIG_SYS_NS16550_SERIAL
  268. #define CONFIG_SYS_NS16550_REG_SIZE 1
  269. #define CONFIG_SYS_BAUDRATE_TABLE \
  270. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  271. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  272. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  273. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  274. #define CONFIG_HAS_FSL_DR_USB
  275. #define CONFIG_SYS_SCCR_USBDRCM 3
  276. /*
  277. * BAT's
  278. */
  279. #define CONFIG_HIGH_BATS
  280. /* DDR @ 0x00000000 */
  281. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
  282. BATL_PP_10)
  283. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
  284. BATU_BL_256M |\
  285. BATU_VS |\
  286. BATU_VP)
  287. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  288. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  289. /* Initial RAM @ 0xFD000000 */
  290. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
  291. BATL_PP_10 |\
  292. BATL_GUARDEDSTORAGE)
  293. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
  294. BATU_BL_256K |\
  295. BATU_VS |\
  296. BATU_VP)
  297. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  298. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  299. /* FLASH @ 0xFF800000 */
  300. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
  301. BATL_PP_10 |\
  302. BATL_GUARDEDSTORAGE)
  303. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
  304. BATU_BL_8M |\
  305. BATU_VS |\
  306. BATU_VP)
  307. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
  308. BATL_PP_10 |\
  309. BATL_CACHEINHIBIT |\
  310. BATL_GUARDEDSTORAGE)
  311. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  312. #define CONFIG_SYS_IBAT3L (0)
  313. #define CONFIG_SYS_IBAT3U (0)
  314. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  315. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  316. #define CONFIG_SYS_IBAT4L (0)
  317. #define CONFIG_SYS_IBAT4U (0)
  318. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  319. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  320. /* IMMRBAR @ 0xF0000000 */
  321. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
  322. BATL_PP_10 |\
  323. BATL_CACHEINHIBIT |\
  324. BATL_GUARDEDSTORAGE)
  325. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
  326. BATU_BL_128M |\
  327. BATU_VS |\
  328. BATU_VP)
  329. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  330. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  331. /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
  332. #define CONFIG_SYS_IBAT6L (0xE0000000 |\
  333. BATL_PP_10 |\
  334. BATL_GUARDEDSTORAGE)
  335. #define CONFIG_SYS_IBAT6U (0xE0000000 |\
  336. BATU_BL_256M |\
  337. BATU_VS |\
  338. BATU_VP)
  339. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  340. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  341. #define CONFIG_SYS_IBAT7L (0)
  342. #define CONFIG_SYS_IBAT7U (0)
  343. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  344. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  345. /*
  346. * U-Boot environment setup
  347. */
  348. #define CONFIG_BOOTP_BOOTFILESIZE
  349. /*
  350. * The reserved memory
  351. */
  352. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  353. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  354. #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
  355. /*
  356. * Environment Configuration
  357. */
  358. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
  359. + CONFIG_SYS_MONITOR_LEN)
  360. #define CONFIG_ENV_SIZE 0x20000
  361. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  362. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  363. #define CONFIG_NETDEV eth1
  364. #define CONFIG_HOSTNAME "ids8313"
  365. #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
  366. #define CONFIG_BOOTFILE "ids8313/uImage"
  367. #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
  368. #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
  369. #define CONFIG_LOADADDR 0x400000
  370. #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
  371. /* Initial Memory map for Linux*/
  372. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  373. /*
  374. * Miscellaneous configurable options
  375. */
  376. #define CONFIG_SYS_CBSIZE 1024
  377. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  378. #define CONFIG_SYS_MEMTEST_START 0x00001000
  379. #define CONFIG_SYS_MEMTEST_END 0x00C00000
  380. #define CONFIG_SYS_LOAD_ADDR 0x100000
  381. #define CONFIG_MII
  382. #define CONFIG_LOADS_ECHO
  383. #define CONFIG_TIMESTAMP
  384. #define CONFIG_PREBOOT "echo;" \
  385. "echo Type \\\"run nfsboot\\\" " \
  386. "to mount root filesystem over NFS;echo"
  387. #define CONFIG_BOOTCOMMAND "run boot_cramfs"
  388. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  389. #define CONFIG_JFFS2_NAND
  390. #define CONFIG_JFFS2_DEV "0"
  391. /* mtdparts command line support */
  392. #define CONFIG_FLASH_CFI_MTD
  393. #define CONFIG_MTD_DEVICE
  394. #define CONFIG_EXTRA_ENV_SETTINGS \
  395. "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  396. "ethprime=TSEC1\0" \
  397. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  398. "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
  399. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  400. " +${filesize}; " \
  401. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  402. " +${filesize}; " \
  403. "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  404. " ${filesize}; " \
  405. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  406. " +${filesize}; " \
  407. "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  408. " ${filesize}\0" \
  409. "console=ttyS0\0" \
  410. "fdtaddr=0x780000\0" \
  411. "kernel_addr=ff800000\0" \
  412. "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
  413. "setbootargs=setenv bootargs " \
  414. "root=${rootdev} rw console=${console}," \
  415. "${baudrate} ${othbootargs}\0" \
  416. "setipargs=setenv bootargs root=${rootdev} rw " \
  417. "nfsroot=${serverip}:${rootpath} " \
  418. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  419. "${netmask}:${hostname}:${netdev}:off " \
  420. "console=${console},${baudrate} ${othbootargs}\0" \
  421. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  422. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  423. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  424. "\0"
  425. #define CONFIG_NFSBOOTCOMMAND \
  426. "setenv rootdev /dev/nfs;" \
  427. "run setipargs;run addmtd;" \
  428. "tftp ${loadaddr} ${bootfile};" \
  429. "tftp ${fdtaddr} ${fdtfile};" \
  430. "fdt addr ${fdtaddr};" \
  431. "bootm ${loadaddr} - ${fdtaddr}"
  432. /* UBI Support */
  433. #define CONFIG_MTD_PARTITIONS
  434. #endif /* __CONFIG_H */