h2200.h 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * iPAQ h2200 board configuration
  4. *
  5. * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #define CONFIG_MACH_TYPE MACH_TYPE_H2200
  10. #define CONFIG_CPU_PXA25X 1
  11. #define CONFIG_NR_DRAM_BANKS 1
  12. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  13. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  14. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  15. #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
  16. #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
  17. #define CONFIG_ENV_SIZE 0x00040000
  18. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
  19. #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
  20. /*
  21. * iPAQ 1st stage bootloader loads 2nd stage bootloader
  22. * at address 0xa0040000 but bootloader requires header
  23. * which is 0x1000 long.
  24. *
  25. * --- Header begin ---
  26. * .word 0xea0003fe ; b 0x1000
  27. *
  28. * .org 0x40
  29. * .ascii "ECEC"
  30. *
  31. * .org 0x1000
  32. * --- Header end ---
  33. */
  34. /*
  35. * Static chips
  36. */
  37. #define CONFIG_SYS_MSC0_VAL 0x246c7ffc
  38. #define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
  39. #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
  40. /*
  41. * PCMCIA and CF Interfaces
  42. */
  43. #define CONFIG_SYS_MECR_VAL 0x00000000
  44. #define CONFIG_SYS_MCMEM0_VAL 0x00000000
  45. #define CONFIG_SYS_MCMEM1_VAL 0x00000000
  46. #define CONFIG_SYS_MCATT0_VAL 0x00000000
  47. #define CONFIG_SYS_MCATT1_VAL 0x00000000
  48. #define CONFIG_SYS_MCIO0_VAL 0x00000000
  49. #define CONFIG_SYS_MCIO1_VAL 0x00000000
  50. #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
  51. #define CONFIG_SYS_SXCNFG_VAL 0x00040004
  52. #define CONFIG_SYS_MDREFR_VAL 0x0099E018
  53. #define CONFIG_SYS_MDCNFG_VAL 0x01C801CB
  54. #define CONFIG_SYS_MDMRS_VAL 0x00220022
  55. #define CONFIG_SYS_PSSR_VAL 0x00000000
  56. #define CONFIG_SYS_CKEN 0x00004840
  57. #define CONFIG_SYS_CCCR 0x00000161
  58. /*
  59. * GPIOs
  60. */
  61. #define CONFIG_SYS_GPSR0_VAL 0x01000000
  62. #define CONFIG_SYS_GPSR1_VAL 0x00000000
  63. #define CONFIG_SYS_GPSR2_VAL 0x00010000
  64. #define CONFIG_SYS_GPCR0_VAL 0x00000000
  65. #define CONFIG_SYS_GPCR1_VAL 0x00000000
  66. #define CONFIG_SYS_GPCR2_VAL 0x00000000
  67. #define CONFIG_SYS_GPDR0_VAL 0xF7E38C00
  68. #define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83
  69. #define CONFIG_SYS_GPDR2_VAL 0x000157FF
  70. #define CONFIG_SYS_GAFR0_L_VAL 0x80401000
  71. #define CONFIG_SYS_GAFR0_U_VAL 0x00000112
  72. #define CONFIG_SYS_GAFR1_L_VAL 0x600A9550
  73. #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
  74. #define CONFIG_SYS_GAFR2_L_VAL 0x20000000
  75. #define CONFIG_SYS_GAFR2_U_VAL 0x00000000
  76. /*
  77. * Serial port
  78. */
  79. #define CONFIG_FFUART
  80. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
  81. #define CONFIG_SETUP_MEMORY_TAGS
  82. #define CONFIG_CMDLINE_TAG
  83. #define CONFIG_INITRD_TAG
  84. /* Monitor Command Prompt */
  85. #define CONFIG_USB_DEV_PULLUP_GPIO 33
  86. /* USB VBUS GPIO 3 */
  87. #define CONFIG_BOOTCOMMAND \
  88. "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
  89. "if bootp ; then setenv downloaded 1 ; fi ; done ; " \
  90. "source :script ; " \
  91. "bootm ; "
  92. #define CONFIG_USB_GADGET_PXA2XX
  93. #define CONFIG_USB_ETH_SUBSET
  94. #define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
  95. #define CONFIG_EXTRA_ENV_SETTINGS \
  96. "stdin=serial\0" \
  97. "stdout=serial\0" \
  98. "stderr=serial\0"
  99. #endif /* __CONFIG_H */