ethernut5.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * egnite GmbH <info@egnite.de>
  5. *
  6. * Configuation settings for Ethernut 5 with AT91SAM9XE.
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <asm/hardware.h>
  11. /* The first stage boot loader expects u-boot running at this address. */
  12. /* The first stage boot loader takes care of low level initialization. */
  13. #define CONFIG_SKIP_LOWLEVEL_INIT
  14. /* Set our official architecture number. */
  15. #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
  16. /* CPU information */
  17. #define CONFIG_ARCH_CPU_INIT
  18. /* ARM asynchronous clock */
  19. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
  20. #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
  21. /* 32kB internal SRAM */
  22. #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
  23. #define CONFIG_SRAM_SIZE (32 << 10)
  24. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
  25. GENERATED_GBL_DATA_SIZE)
  26. /* 128MB SDRAM in 1 bank */
  27. #define CONFIG_NR_DRAM_BANKS 1
  28. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  29. #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
  30. #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
  31. #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
  32. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
  33. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  34. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
  35. - CONFIG_SYS_MALLOC_LEN)
  36. /* 512kB on-chip NOR flash */
  37. # define CONFIG_SYS_MAX_FLASH_BANKS 1
  38. # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
  39. # define CONFIG_AT91_EFLASH
  40. # define CONFIG_SYS_MAX_FLASH_SECT 32
  41. # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
  42. # define CONFIG_EFLASH_PROTSECTORS 1
  43. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  44. #define CONFIG_ENV_OFFSET 0x3DE000
  45. #define CONFIG_ENV_SIZE (132 << 10)
  46. #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
  47. #define CONFIG_ENV_SPI_MAX_HZ 15000000
  48. #ifndef MINIMAL_LOADER
  49. #endif
  50. /* NAND flash */
  51. #ifdef CONFIG_CMD_NAND
  52. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  53. #define CONFIG_SYS_NAND_BASE 0x40000000
  54. #define CONFIG_SYS_NAND_DBW_8
  55. #define CONFIG_NAND_ATMEL
  56. /* our ALE is AD21 */
  57. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  58. /* our CLE is AD22 */
  59. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  60. #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
  61. #endif
  62. /* JFFS2 */
  63. #ifdef CONFIG_CMD_JFFS2
  64. #define CONFIG_JFFS2_CMDLINE
  65. #define CONFIG_JFFS2_NAND
  66. #endif
  67. /* Ethernet */
  68. #define CONFIG_NET_RETRY_COUNT 20
  69. #define CONFIG_MACB
  70. #define CONFIG_RMII
  71. #define CONFIG_PHY_ID 0
  72. #define CONFIG_MACB_SEARCH_PHY
  73. /* MMC */
  74. #ifdef CONFIG_CMD_MMC
  75. #define CONFIG_GENERIC_ATMEL_MCI
  76. #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
  77. #endif
  78. /* USB */
  79. #ifdef CONFIG_CMD_USB
  80. #define CONFIG_USB_ATMEL
  81. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  82. #define CONFIG_USB_OHCI_NEW
  83. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  84. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
  85. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
  86. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  87. #endif
  88. /* RTC */
  89. #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
  90. #define CONFIG_RTC_PCF8563
  91. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  92. #endif
  93. /* I2C */
  94. #define CONFIG_SYS_MAX_I2C_BUS 1
  95. #define CONFIG_SYS_I2C
  96. #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  97. #define CONFIG_SYS_I2C_SOFT_SPEED 100000
  98. #define CONFIG_SYS_I2C_SOFT_SLAVE 0
  99. #define I2C_SOFT_DECLARATIONS
  100. #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
  101. #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
  102. #define I2C_INIT { \
  103. at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
  104. at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
  105. at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
  106. at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
  107. at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
  108. }
  109. #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
  110. #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
  111. #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
  112. #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
  113. #define I2C_DELAY udelay(100)
  114. #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
  115. /* DHCP/BOOTP options */
  116. #ifdef CONFIG_CMD_DHCP
  117. #define CONFIG_BOOTP_BOOTFILESIZE
  118. #define CONFIG_SYS_AUTOLOAD "n"
  119. #endif
  120. /* File systems */
  121. #define CONFIG_MTD_DEVICE
  122. #define CONFIG_MTD_PARTITIONS
  123. /* Boot command */
  124. #define CONFIG_CMDLINE_TAG
  125. #define CONFIG_SETUP_MEMORY_TAGS
  126. #define CONFIG_INITRD_TAG
  127. #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
  128. "sf read 0x22000000 0xc6000 0x294000; " \
  129. "bootm 0x22000000"
  130. /* Misc. u-boot settings */
  131. #endif