ecovec.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Renesas Solutions ECOVEC board
  4. *
  5. * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
  6. * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  8. */
  9. #ifndef __ECOVEC_H
  10. #define __ECOVEC_H
  11. /*
  12. * Address Interface BusWidth
  13. *-----------------------------------------
  14. * 0x0000_0000 U-Boot 16bit
  15. * 0x0004_0000 Linux romImage 16bit
  16. * 0x0014_0000 MTD for Linux 16bit
  17. * 0x0400_0000 Internal I/O 16/32bit
  18. * 0x0800_0000 DRAM 32bit
  19. * 0x1800_0000 MFI 16bit
  20. */
  21. #define CONFIG_CPU_SH7724 1
  22. #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
  23. #define CONFIG_DISPLAY_BOARDINFO
  24. #undef CONFIG_SHOW_BOOT_PROGRESS
  25. /* I2C */
  26. #define CONFIG_SYS_I2C
  27. #define CONFIG_SYS_I2C_SH
  28. #define CONFIG_SYS_I2C_SLAVE 0x7F
  29. #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
  30. #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
  31. #define CONFIG_SYS_I2C_SH_SPEED0 100000
  32. #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
  33. #define CONFIG_SYS_I2C_SH_SPEED1 100000
  34. #define CONFIG_SH_I2C_DATA_HIGH 4
  35. #define CONFIG_SH_I2C_DATA_LOW 5
  36. #define CONFIG_SH_I2C_CLOCK 41666666
  37. /* Ether */
  38. #define CONFIG_SH_ETHER_USE_PORT (0)
  39. #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
  40. #define CONFIG_PHY_SMSC 1
  41. #define CONFIG_BITBANGMII
  42. #define CONFIG_BITBANGMII_MULTI
  43. #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  44. /* USB / R8A66597 */
  45. #define CONFIG_USB_R8A66597_HCD
  46. #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
  47. #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
  48. #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
  49. #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
  50. #define CONFIG_SUPERH_ON_CHIP_R8A66597
  51. /* undef to save memory */
  52. /* Monitor Command Prompt */
  53. /* Buffer size for Console output */
  54. #define CONFIG_SYS_PBSIZE 256
  55. /* List of legal baudrate settings for this board */
  56. #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  57. /* SCIF */
  58. #define CONFIG_SCIF 1
  59. #define CONFIG_CONS_SCIF0 1
  60. /* Suppress display of console information at boot */
  61. /* SDRAM */
  62. #define CONFIG_SYS_SDRAM_BASE (0x88000000)
  63. #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
  64. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  65. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
  66. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
  67. /* Enable alternate, more extensive, memory test */
  68. /* Scratch address used by the alternate memory test */
  69. #undef CONFIG_SYS_MEMTEST_SCRATCH
  70. /* Enable temporary baudrate change while serial download */
  71. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  72. /* FLASH */
  73. #define CONFIG_FLASH_CFI_DRIVER 1
  74. #define CONFIG_SYS_FLASH_CFI
  75. #undef CONFIG_SYS_FLASH_QUIET_TEST
  76. #define CONFIG_SYS_FLASH_EMPTY_INFO
  77. #define CONFIG_SYS_FLASH_BASE (0xA0000000)
  78. #define CONFIG_SYS_MAX_FLASH_SECT 512
  79. /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
  80. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  81. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  82. /* Timeout for Flash erase operations (in ms) */
  83. #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
  84. /* Timeout for Flash write operations (in ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
  86. /* Timeout for Flash set sector lock bit operations (in ms) */
  87. #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
  88. /* Timeout for Flash clear lock bit operations (in ms) */
  89. #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
  90. /*
  91. * Use hardware flash sectors protection instead
  92. * of U-Boot software protection
  93. */
  94. #undef CONFIG_SYS_FLASH_PROTECTION
  95. #undef CONFIG_SYS_DIRECT_FLASH_TFTP
  96. /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
  97. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
  98. /* Monitor size */
  99. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  100. /* Size of DRAM reserved for malloc() use */
  101. #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
  102. #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  103. /* ENV setting */
  104. #define CONFIG_ENV_OVERWRITE 1
  105. #define CONFIG_ENV_SECT_SIZE (128 * 1024)
  106. #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  107. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  108. /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
  109. #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
  110. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
  111. /* Board Clock */
  112. #define CONFIG_SYS_CLK_FREQ 41666666
  113. #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  114. #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  115. #define CONFIG_SYS_TMU_CLK_DIV 4
  116. #endif /* __ECOVEC_H */