devkit3250.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Embest/Timll DevKit3250 board configuration file
  4. *
  5. * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  6. */
  7. #ifndef __CONFIG_DEVKIT3250_H__
  8. #define __CONFIG_DEVKIT3250_H__
  9. /* SoC and board defines */
  10. #include <linux/sizes.h>
  11. #include <asm/arch/cpu.h>
  12. #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
  13. #define CONFIG_SYS_ICACHE_OFF
  14. #define CONFIG_SYS_DCACHE_OFF
  15. #if !defined(CONFIG_SPL_BUILD)
  16. #define CONFIG_SKIP_LOWLEVEL_INIT
  17. #endif
  18. /*
  19. * Memory configurations
  20. */
  21. #define CONFIG_NR_DRAM_BANKS 1
  22. #define CONFIG_SYS_MALLOC_LEN SZ_1M
  23. #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
  24. #define CONFIG_SYS_SDRAM_SIZE SZ_64M
  25. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  26. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
  27. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  28. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  29. - GENERATED_GBL_DATA_SIZE)
  30. /*
  31. * Serial Driver
  32. */
  33. #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
  34. /*
  35. * DMA
  36. */
  37. #if !defined(CONFIG_SPL_BUILD)
  38. #define CONFIG_DMA_LPC32XX
  39. #endif
  40. /*
  41. * I2C
  42. */
  43. #define CONFIG_SYS_I2C
  44. #define CONFIG_SYS_I2C_LPC32XX
  45. #define CONFIG_SYS_I2C_SPEED 100000
  46. /*
  47. * GPIO
  48. */
  49. #define CONFIG_LPC32XX_GPIO
  50. /*
  51. * SSP/SPI
  52. */
  53. #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
  54. /*
  55. * Ethernet
  56. */
  57. #define CONFIG_RMII
  58. #define CONFIG_PHY_SMSC
  59. #define CONFIG_LPC32XX_ETH
  60. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  61. /*
  62. * NOR Flash
  63. */
  64. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  65. #define CONFIG_SYS_MAX_FLASH_SECT 71
  66. #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
  67. #define CONFIG_SYS_FLASH_SIZE SZ_4M
  68. #define CONFIG_SYS_FLASH_CFI
  69. /*
  70. * NAND controller
  71. */
  72. #define CONFIG_NAND_LPC32XX_SLC
  73. #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
  74. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  75. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  76. /*
  77. * NAND chip timings
  78. */
  79. #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
  80. #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
  81. #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
  82. #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
  83. #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
  84. #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
  85. #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
  86. #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
  87. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  88. #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
  89. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  90. /*
  91. * USB
  92. */
  93. #define CONFIG_USB_OHCI_LPC32XX
  94. #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
  95. /*
  96. * U-Boot General Configurations
  97. */
  98. #define CONFIG_SYS_CBSIZE 1024
  99. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  100. /*
  101. * Pass open firmware flat tree
  102. */
  103. /*
  104. * Environment
  105. */
  106. #define CONFIG_ENV_SIZE SZ_128K
  107. #define CONFIG_ENV_OFFSET 0x000A0000
  108. #define CONFIG_BOOTCOMMAND \
  109. "dhcp; " \
  110. "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
  111. "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
  112. "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
  113. "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
  114. "bootm ${loadaddr} - ${dtbaddr}"
  115. #define CONFIG_EXTRA_ENV_SETTINGS \
  116. "autoload=no\0" \
  117. "ethaddr=00:01:90:00:C0:81\0" \
  118. "dtbaddr=0x81000000\0" \
  119. "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
  120. "tftpdir=vladimir/oe/devkit3250\0" \
  121. "userargs=oops=panic\0"
  122. /*
  123. * U-Boot Commands
  124. */
  125. /*
  126. * Boot Linux
  127. */
  128. #define CONFIG_CMDLINE_TAG
  129. #define CONFIG_SETUP_MEMORY_TAGS
  130. #define CONFIG_BOOTFILE "uImage"
  131. #define CONFIG_LOADADDR 0x80008000
  132. /*
  133. * SPL specific defines
  134. */
  135. /* SPL will be executed at offset 0 */
  136. #define CONFIG_SPL_TEXT_BASE 0x00000000
  137. /* SPL will use SRAM as stack */
  138. #define CONFIG_SPL_STACK 0x0000FFF8
  139. /* Use the framework and generic lib */
  140. /* SPL will use serial */
  141. /* SPL loads an image from NAND */
  142. #define CONFIG_SPL_NAND_RAW_ONLY
  143. #define CONFIG_SPL_NAND_DRIVERS
  144. #define CONFIG_SPL_NAND_ECC
  145. #define CONFIG_SPL_NAND_SOFTECC
  146. #define CONFIG_SPL_MAX_SIZE 0x20000
  147. #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
  148. /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
  149. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  150. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
  151. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  152. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  153. /* See common/spl/spl.c spl_set_header_raw_uboot() */
  154. #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
  155. /*
  156. * Include SoC specific configuration
  157. */
  158. #include <asm/arch/config.h>
  159. #endif /* __CONFIG_DEVKIT3250_H__*/