db-mv784mp-gp.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  4. */
  5. #ifndef _CONFIG_DB_MV7846MP_GP_H
  6. #define _CONFIG_DB_MV7846MP_GP_H
  7. /*
  8. * High Level Configuration Options (easy to change)
  9. */
  10. #define CONFIG_DB_784MP_GP /* Board target name for DDR training */
  11. /*
  12. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  13. * for DDR ECC byte filling in the SPL before loading the main
  14. * U-Boot into it.
  15. */
  16. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  17. /* I2C */
  18. #define CONFIG_SYS_I2C
  19. #define CONFIG_SYS_I2C_MVTWSI
  20. #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
  21. #define CONFIG_SYS_I2C_SLAVE 0x0
  22. #define CONFIG_SYS_I2C_SPEED 100000
  23. /* USB/EHCI configuration */
  24. #define CONFIG_EHCI_IS_TDI
  25. #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  26. /* SPI NOR flash default params, used by sf commands */
  27. #define CONFIG_SF_DEFAULT_SPEED 1000000
  28. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
  29. /* Environment in SPI NOR flash */
  30. #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
  31. #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
  32. #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
  33. #define CONFIG_PHY_MARVELL /* there is a marvell phy */
  34. #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
  35. /* SATA support */
  36. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  37. #define CONFIG_LBA48
  38. /* PCIe support */
  39. #ifndef CONFIG_SPL_BUILD
  40. #define CONFIG_PCI_MVEBU
  41. #define CONFIG_PCI_SCAN_SHOW
  42. #endif
  43. /* NAND */
  44. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  45. #define CONFIG_SYS_NAND_ONFI_DETECTION
  46. /*
  47. * mv-common.h should be defined after CMD configs since it used them
  48. * to enable certain macros
  49. */
  50. #include "mv-common.h"
  51. /*
  52. * Memory layout while starting into the bin_hdr via the
  53. * BootROM:
  54. *
  55. * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
  56. * 0x4000.4030 bin_hdr start address
  57. * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
  58. * 0x4007.fffc BootROM stack top
  59. *
  60. * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  61. * L2 cache thus cannot be used.
  62. */
  63. /* SPL */
  64. /* Defines for SPL */
  65. #define CONFIG_SPL_TEXT_BASE 0x40004030
  66. #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
  67. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
  68. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  69. #ifdef CONFIG_SPL_BUILD
  70. #define CONFIG_SYS_MALLOC_SIMPLE
  71. #endif
  72. #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
  73. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  74. /* SPL related SPI defines */
  75. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
  76. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
  77. /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  78. #define CONFIG_SPD_EEPROM 0x4e
  79. #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
  80. #endif /* _CONFIG_DB_MV7846MP_GP_H */