da850evm.h 8.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on davinci_dvevm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * Board
  13. */
  14. #define CONFIG_DRIVER_TI_EMAC
  15. /* check if direct NOR boot config is used */
  16. #ifndef CONFIG_DIRECT_NOR_BOOT
  17. #define CONFIG_USE_SPIFLASH
  18. #endif
  19. /*
  20. * Disable DM_* for SPL build and can be re-enabled after adding
  21. * DM support in SPL
  22. */
  23. #ifdef CONFIG_SPL_BUILD
  24. #undef CONFIG_DM_SPI
  25. #undef CONFIG_DM_SPI_FLASH
  26. #undef CONFIG_DM_I2C
  27. #undef CONFIG_DM_I2C_COMPAT
  28. #endif
  29. /*
  30. * SoC Configuration
  31. */
  32. #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  33. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  34. #define CONFIG_SYS_OSCIN_FREQ 24000000
  35. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  36. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  37. #ifdef CONFIG_DIRECT_NOR_BOOT
  38. #define CONFIG_ARCH_CPU_INIT
  39. #define CONFIG_DA8XX_GPIO
  40. #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
  41. #endif
  42. /*
  43. * Memory Info
  44. */
  45. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  46. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  47. #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
  48. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  49. /* memtest start addr */
  50. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  51. /* memtest will be run on 16MB */
  52. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  53. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  54. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  55. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  56. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  57. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  58. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  59. DAVINCI_SYSCFG_SUSPSRC_I2C)
  60. /*
  61. * PLL configuration
  62. */
  63. #define CONFIG_SYS_DA850_PLL0_PLLM 24
  64. #define CONFIG_SYS_DA850_PLL1_PLLM 21
  65. /*
  66. * DDR2 memory configuration
  67. */
  68. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  69. DV_DDR_PHY_EXT_STRBEN | \
  70. (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  71. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  72. (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
  73. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  74. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  75. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  76. (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
  77. (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
  78. (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  79. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  80. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  81. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  82. (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  83. (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
  84. (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  85. (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
  86. (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  87. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  88. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  89. (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  90. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  91. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  92. (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
  93. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  94. (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  95. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  96. (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  97. (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  98. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
  99. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  100. /*
  101. * Serial Driver info
  102. */
  103. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
  104. #define CONFIG_SYS_NS16550_SERIAL
  105. #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
  106. #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
  107. #endif
  108. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  109. #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
  110. #ifdef CONFIG_SPL_BUILD
  111. #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
  112. #define CONFIG_SF_DEFAULT_SPEED 30000000
  113. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  114. #endif
  115. #ifdef CONFIG_USE_SPIFLASH
  116. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
  117. #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
  118. #endif
  119. /*
  120. * I2C Configuration
  121. */
  122. #ifndef CONFIG_SPL_BUILD
  123. #define CONFIG_SYS_I2C_DAVINCI
  124. #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
  125. #endif
  126. /*
  127. * Flash & Environment
  128. */
  129. #ifdef CONFIG_USE_NAND
  130. #define CONFIG_NAND_DAVINCI
  131. #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
  132. #define CONFIG_ENV_SIZE (128 << 10)
  133. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  134. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  135. #define CONFIG_SYS_NAND_PAGE_2K
  136. #define CONFIG_SYS_NAND_CS 3
  137. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  138. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  139. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  140. #undef CONFIG_SYS_NAND_HW_ECC
  141. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  142. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  143. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  144. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  145. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  146. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
  147. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
  148. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  149. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  150. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  151. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  152. CONFIG_SYS_MALLOC_LEN - \
  153. GENERATED_GBL_DATA_SIZE)
  154. #define CONFIG_SYS_NAND_ECCPOS { \
  155. 24, 25, 26, 27, 28, \
  156. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
  157. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
  158. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
  159. 59, 60, 61, 62, 63 }
  160. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  161. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  162. #define CONFIG_SYS_NAND_ECCSIZE 512
  163. #define CONFIG_SYS_NAND_ECCBYTES 10
  164. #define CONFIG_SYS_NAND_OOBSIZE 64
  165. #define CONFIG_SPL_NAND_BASE
  166. #define CONFIG_SPL_NAND_DRIVERS
  167. #define CONFIG_SPL_NAND_ECC
  168. #define CONFIG_SPL_NAND_LOAD
  169. #endif
  170. /*
  171. * Network & Ethernet Configuration
  172. */
  173. #ifdef CONFIG_DRIVER_TI_EMAC
  174. #define CONFIG_MII
  175. #define CONFIG_BOOTP_DNS2
  176. #define CONFIG_BOOTP_SEND_HOSTNAME
  177. #define CONFIG_NET_RETRY_COUNT 10
  178. #endif
  179. #ifdef CONFIG_USE_NOR
  180. #define CONFIG_FLASH_CFI_DRIVER
  181. #define CONFIG_SYS_FLASH_CFI
  182. #define CONFIG_SYS_FLASH_PROTECTION
  183. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  184. #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
  185. #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
  186. #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
  187. #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
  188. #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
  189. #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
  190. + 3)
  191. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
  192. #endif
  193. #ifdef CONFIG_USE_SPIFLASH
  194. #define CONFIG_ENV_SIZE (64 << 10)
  195. #define CONFIG_ENV_OFFSET (512 << 10)
  196. #define CONFIG_ENV_SECT_SIZE (64 << 10)
  197. #ifdef CONFIG_SPL_BUILD
  198. #undef CONFIG_SPI_FLASH_MTD
  199. #endif
  200. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  201. #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
  202. #endif
  203. /*
  204. * U-Boot general configuration
  205. */
  206. #define CONFIG_MISC_INIT_R
  207. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  208. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  209. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  210. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  211. #define CONFIG_MX_CYCLIC
  212. /*
  213. * Linux Information
  214. */
  215. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  216. #define CONFIG_HWCONFIG /* enable hwconfig */
  217. #define CONFIG_CMDLINE_TAG
  218. #define CONFIG_REVISION_TAG
  219. #define CONFIG_SETUP_MEMORY_TAGS
  220. #define CONFIG_BOOTCOMMAND \
  221. "run envboot; " \
  222. "run mmcboot; "
  223. #define DEFAULT_LINUX_BOOT_ENV \
  224. "loadaddr=0xc0700000\0" \
  225. "fdtaddr=0xc0600000\0" \
  226. "scriptaddr=0xc0600000\0"
  227. #include <environment/ti/mmc.h>
  228. #define CONFIG_EXTRA_ENV_SETTINGS \
  229. DEFAULT_LINUX_BOOT_ENV \
  230. DEFAULT_MMC_TI_ARGS \
  231. "bootpart=0:2\0" \
  232. "bootdir=/boot\0" \
  233. "bootfile=zImage\0" \
  234. "fdtfile=da850-evm.dtb\0" \
  235. "boot_fdt=yes\0" \
  236. "boot_fit=0\0" \
  237. "console=ttyS2,115200n8\0" \
  238. "hwconfig=dsp:wake=yes"
  239. #ifdef CONFIG_CMD_BDI
  240. #define CONFIG_CLOCKS
  241. #endif
  242. #ifdef CONFIG_USE_NAND
  243. #define CONFIG_MTD_DEVICE
  244. #define CONFIG_MTD_PARTITIONS
  245. #endif
  246. #if !defined(CONFIG_USE_NAND) && \
  247. !defined(CONFIG_USE_NOR) && \
  248. !defined(CONFIG_USE_SPIFLASH)
  249. #define CONFIG_ENV_SIZE (16 << 10)
  250. #endif
  251. #ifndef CONFIG_DIRECT_NOR_BOOT
  252. /* defines for SPL */
  253. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  254. CONFIG_SYS_MALLOC_LEN)
  255. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  256. #define CONFIG_SPL_STACK 0x8001ff00
  257. #define CONFIG_SPL_TEXT_BASE 0x80000000
  258. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  259. #define CONFIG_SPL_PAD_TO 32768
  260. #endif
  261. /* Load U-Boot Image From MMC */
  262. /* additions for new relocation code, must added to all boards */
  263. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  264. #ifdef CONFIG_DIRECT_NOR_BOOT
  265. #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
  266. #else
  267. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  268. GENERATED_GBL_DATA_SIZE)
  269. #endif /* CONFIG_DIRECT_NOR_BOOT */
  270. #include <asm/arch/hardware.h>
  271. #endif /* __CONFIG_H */