colibri_pxa270.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Toradex Colibri PXA270 configuration file
  4. *
  5. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  6. * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Board Configuration Options
  12. */
  13. #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
  14. /* Avoid overwriting factory configuration block */
  15. #define CONFIG_BOARD_SIZE_LIMIT 0x40000
  16. /* We will never enable dcache because we have to setup MMU first */
  17. #define CONFIG_SYS_DCACHE_OFF
  18. /*
  19. * Environment settings
  20. */
  21. #define CONFIG_ENV_OVERWRITE
  22. #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
  23. #define CONFIG_ARCH_CPU_INIT
  24. #define CONFIG_BOOTCOMMAND \
  25. "if fatload mmc 0 0xa0000000 uImage; then " \
  26. "bootm 0xa0000000; " \
  27. "fi; " \
  28. "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
  29. "bootm 0xa0000000; " \
  30. "fi; " \
  31. "bootm 0xc0000;"
  32. #define CONFIG_TIMESTAMP
  33. #define CONFIG_CMDLINE_TAG
  34. #define CONFIG_SETUP_MEMORY_TAGS
  35. /*
  36. * Serial Console Configuration
  37. */
  38. /*
  39. * Bootloader Components Configuration
  40. */
  41. /* I2C support */
  42. #ifdef CONFIG_SYS_I2C
  43. #define CONFIG_SYS_I2C_PXA
  44. #define CONFIG_PXA_STD_I2C
  45. #define CONFIG_PXA_PWR_I2C
  46. #define CONFIG_SYS_I2C_SPEED 100000
  47. #endif
  48. /* LCD support */
  49. #ifdef CONFIG_LCD
  50. #define CONFIG_PXA_LCD
  51. #define CONFIG_PXA_VGA
  52. #define CONFIG_LCD_LOGO
  53. #endif
  54. /*
  55. * Networking Configuration
  56. */
  57. #ifdef CONFIG_CMD_NET
  58. #define CONFIG_DRIVER_DM9000 1
  59. #define CONFIG_DM9000_BASE 0x08000000
  60. #define DM9000_IO (CONFIG_DM9000_BASE)
  61. #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  62. #define CONFIG_NET_RETRY_COUNT 10
  63. #define CONFIG_BOOTP_BOOTFILESIZE
  64. #endif
  65. #define CONFIG_SYS_DEVICE_NULLDEV 1
  66. /*
  67. * Clock Configuration
  68. */
  69. #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
  70. /*
  71. * DRAM Map
  72. */
  73. #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
  74. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  75. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  76. #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
  77. #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
  78. #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
  79. #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  80. #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
  81. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  82. #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
  83. /*
  84. * NOR FLASH
  85. */
  86. #ifdef CONFIG_CMD_FLASH
  87. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  88. #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
  89. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  90. #define CONFIG_SYS_FLASH_CFI
  91. #define CONFIG_FLASH_CFI_DRIVER 1
  92. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  93. #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
  94. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  95. #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
  96. #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
  97. #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
  98. #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
  99. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  100. #define CONFIG_SYS_FLASH_PROTECTION 1
  101. #endif
  102. #define CONFIG_SYS_MONITOR_BASE 0x0
  103. #define CONFIG_SYS_MONITOR_LEN 0x40000
  104. /* Skip factory configuration block */
  105. #define CONFIG_ENV_ADDR \
  106. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
  107. #define CONFIG_ENV_SIZE 0x40000
  108. #define CONFIG_ENV_SECT_SIZE 0x40000
  109. /*
  110. * GPIO settings
  111. */
  112. #define CONFIG_SYS_GPSR0_VAL 0x00000000
  113. #define CONFIG_SYS_GPSR1_VAL 0x00020000
  114. #define CONFIG_SYS_GPSR2_VAL 0x0002c000
  115. #define CONFIG_SYS_GPSR3_VAL 0x00000000
  116. #define CONFIG_SYS_GPCR0_VAL 0x00000000
  117. #define CONFIG_SYS_GPCR1_VAL 0x00000000
  118. #define CONFIG_SYS_GPCR2_VAL 0x00000000
  119. #define CONFIG_SYS_GPCR3_VAL 0x00000000
  120. #define CONFIG_SYS_GPDR0_VAL 0xc8008000
  121. #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
  122. #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
  123. #define CONFIG_SYS_GPDR3_VAL 0x0061e804
  124. #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
  125. #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
  126. #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
  127. #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
  128. #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
  129. #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
  130. #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
  131. #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
  132. #define CONFIG_SYS_PSSR_VAL 0x30
  133. /*
  134. * Clock settings
  135. */
  136. #define CONFIG_SYS_CKEN 0x00500240
  137. #define CONFIG_SYS_CCCR 0x02000290
  138. /*
  139. * Memory settings
  140. */
  141. #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
  142. #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
  143. #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
  144. #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
  145. #define CONFIG_SYS_MDREFR_VAL 0x2003a031
  146. #define CONFIG_SYS_MDMRS_VAL 0x00220022
  147. #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
  148. #define CONFIG_SYS_SXCNFG_VAL 0x40044004
  149. /*
  150. * PCMCIA and CF Interfaces
  151. */
  152. #define CONFIG_SYS_MECR_VAL 0x00000000
  153. #define CONFIG_SYS_MCMEM0_VAL 0x00028307
  154. #define CONFIG_SYS_MCMEM1_VAL 0x00014307
  155. #define CONFIG_SYS_MCATT0_VAL 0x00038787
  156. #define CONFIG_SYS_MCATT1_VAL 0x0001c787
  157. #define CONFIG_SYS_MCIO0_VAL 0x0002830f
  158. #define CONFIG_SYS_MCIO1_VAL 0x0001430f
  159. #include "pxa-common.h"
  160. #endif /* __CONFIG_H */