calimain.h 8.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011-2014 OMICRON electronics GmbH
  4. *
  5. * Based on da850evm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  8. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * Board
  14. */
  15. #define CONFIG_DRIVER_TI_EMAC
  16. #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
  17. /*
  18. * SoC Configuration
  19. */
  20. #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  22. #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
  23. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  24. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  25. #define CONFIG_ARCH_CPU_INIT
  26. #define CONFIG_DA8XX_GPIO
  27. #define CONFIG_HW_WATCHDOG
  28. #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
  29. #define CONFIG_SYS_WDT_PERIOD_LOW \
  30. (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
  31. #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
  32. #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
  33. /*
  34. * PLL configuration
  35. */
  36. #define CONFIG_SYS_DA850_PLL0_PLLM \
  37. ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
  38. #define CONFIG_SYS_DA850_PLL1_PLLM \
  39. ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
  40. /*
  41. * DDR2 memory configuration
  42. */
  43. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  44. DV_DDR_PHY_EXT_STRBEN | \
  45. (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  46. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  47. (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
  48. (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
  49. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  50. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  51. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  52. (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
  53. (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
  54. (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  55. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  56. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  57. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  58. (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  59. (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
  60. (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  61. (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
  62. (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  63. (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
  64. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  65. (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  66. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  67. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  68. (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
  69. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  70. (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  71. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  72. (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  73. (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  74. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
  75. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  76. /*
  77. * Flash memory timing
  78. */
  79. #define CONFIG_SYS_DA850_CS2CFG ( \
  80. DAVINCI_ABCR_WSETUP(2) | \
  81. DAVINCI_ABCR_WSTROBE(5) | \
  82. DAVINCI_ABCR_WHOLD(3) | \
  83. DAVINCI_ABCR_RSETUP(1) | \
  84. DAVINCI_ABCR_RSTROBE(14) | \
  85. DAVINCI_ABCR_RHOLD(0) | \
  86. DAVINCI_ABCR_TA(3) | \
  87. DAVINCI_ABCR_ASIZE_16BIT)
  88. /* single 64 MB NOR flash device connected to CS2 and CS3 */
  89. #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
  90. /*
  91. * Memory Info
  92. */
  93. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  94. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  95. #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
  96. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  97. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  98. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  99. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  100. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  101. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  102. DAVINCI_SYSCFG_SUSPSRC_I2C)
  103. /* memtest start addr */
  104. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  105. /* memtest will be run on 16MB */
  106. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
  107. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  108. /*
  109. * Serial Driver info
  110. */
  111. #define CONFIG_SYS_NS16550_SERIAL
  112. #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
  113. #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
  114. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  115. #define CONFIG_FLASH_CFI_DRIVER
  116. #define CONFIG_SYS_FLASH_CFI
  117. #define CONFIG_SYS_FLASH_PROTECTION
  118. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  119. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  120. #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
  121. #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
  122. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
  123. #define CONFIG_ENV_ADDR \
  124. (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
  125. #define CONFIG_ENV_SIZE (128 << 10)
  126. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  127. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  128. #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
  129. #define CONFIG_SYS_MAX_FLASH_SECT \
  130. ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
  131. /*
  132. * Network & Ethernet Configuration
  133. */
  134. #ifdef CONFIG_DRIVER_TI_EMAC
  135. #define CONFIG_MII
  136. #define CONFIG_BOOTP_DNS2
  137. #define CONFIG_BOOTP_SEND_HOSTNAME
  138. #define CONFIG_NET_RETRY_COUNT 10
  139. #endif
  140. /*
  141. * U-Boot general configuration
  142. */
  143. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  144. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  145. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  146. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  147. #define CONFIG_LOADADDR 0xc0700000
  148. #define CONFIG_MX_CYCLIC
  149. /*
  150. * Linux Information
  151. */
  152. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  153. #define CONFIG_CMDLINE_TAG
  154. #define CONFIG_REVISION_TAG
  155. #define CONFIG_SETUP_MEMORY_TAGS
  156. #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
  157. #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
  158. #define CONFIG_RESET_TO_RETRY
  159. /*
  160. * Default environment settings
  161. * gpio0 = button, gpio1 = led green, gpio2 = led red
  162. * verify = n ... disable kernel checksum verification for faster booting
  163. */
  164. #define CONFIG_EXTRA_ENV_SETTINGS \
  165. "tftpdir=calimero\0" \
  166. "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
  167. "erase 0x60800000 +0x400000; " \
  168. "cp.b $loadaddr 0x60800000 $filesize\0" \
  169. "flashrootfs=" \
  170. "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
  171. "erase 0x60c00000 +0x2e00000; " \
  172. "cp.b $loadaddr 0x60c00000 $filesize\0" \
  173. "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
  174. "protect off all; " \
  175. "erase 0x60000000 +0x80000; " \
  176. "cp.b $loadaddr 0x60000000 $filesize\0" \
  177. "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
  178. "erase 0x60080000 +0x780000; " \
  179. "cp.b $loadaddr 0x60080000 $filesize\0" \
  180. "erase_persistent=erase 0x63a00000 +0x600000;\0" \
  181. "bootnor=setenv bootargs console=ttyS2,115200n8 " \
  182. "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
  183. "rootwait ethaddr=$ethaddr; " \
  184. "gpio c 1; gpio s 2; bootm 0x60800000\0" \
  185. "bootrlk=gpio s 1; gpio s 2;" \
  186. "setenv bootargs console=ttyS2,115200n8 " \
  187. "ethaddr=$ethaddr; bootm 0x60080000\0" \
  188. "boottftp=setenv bootargs console=ttyS2,115200n8 " \
  189. "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
  190. "rootwait ethaddr=$ethaddr; " \
  191. "tftpboot $loadaddr $tftpdir/uImage;" \
  192. "gpio c 1; gpio s 2; bootm $loadaddr\0" \
  193. "checkupdate=if test -n $update_flag; then " \
  194. "echo Previous update failed - starting RLK; " \
  195. "run bootrlk; fi; " \
  196. "if test -n $initial_setup; then " \
  197. "echo Running initial setup procedure; " \
  198. "sleep 1; run flashall; fi\0" \
  199. "product=accessory\0" \
  200. "serial=XX12345\0" \
  201. "checknor=" \
  202. "if gpio i 0; then run bootnor; fi;\0" \
  203. "checkrlk=" \
  204. "if gpio i 0; then run bootrlk; fi;\0" \
  205. "checkbutton=" \
  206. "run checknor; sleep 1;" \
  207. "run checknor; sleep 1;" \
  208. "run checknor; sleep 1;" \
  209. "run checknor; sleep 1;" \
  210. "run checknor;" \
  211. "gpio s 1; gpio s 2;" \
  212. "echo ---- Release button to boot RLK ----;" \
  213. "run checkrlk; sleep 1;" \
  214. "run checkrlk; sleep 1;" \
  215. "run checkrlk; sleep 1;" \
  216. "run checkrlk; sleep 1;" \
  217. "run checkrlk; sleep 1;" \
  218. "run checkrlk;" \
  219. "echo ---- Factory reset requested ----;" \
  220. "gpio c 1;" \
  221. "setenv factory_reset true;" \
  222. "saveenv;" \
  223. "run bootnor;\0" \
  224. "flashall=run flashrlk;" \
  225. "run flashkernel;" \
  226. "run flashrootfs;" \
  227. "setenv erase_datafs true;" \
  228. "setenv initial_setup;" \
  229. "saveenv;" \
  230. "run bootnor;\0" \
  231. "verify=n\0" \
  232. "clearenv=protect off all;" \
  233. "erase 0x60040000 +0x40000;\0" \
  234. "bootlimit=3\0" \
  235. "altbootcmd=run bootrlk\0"
  236. #define CONFIG_PREBOOT \
  237. "echo Version: $ver; " \
  238. "echo Serial: $serial; " \
  239. "echo MAC: $ethaddr; " \
  240. "echo Product: $product; " \
  241. "gpio c 1; gpio c 2;"
  242. /* additions for new relocation code, must added to all boards */
  243. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  244. /* initial stack pointer in internal SRAM */
  245. #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
  246. #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
  247. #ifndef __ASSEMBLY__
  248. int calimain_get_osc_freq(void);
  249. #endif
  250. #include <asm/arch/hardware.h>
  251. #endif /* __CONFIG_H */