am3517_crane.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * am3517_crane.h - Default configuration for AM3517 CraneBoard.
  4. *
  5. * Author: Srinath.R <srinath@mistralsolutions.com>
  6. *
  7. * Based on include/configs/am3517evm.h
  8. *
  9. * Copyright (C) 2011 Mistral Solutions pvt Ltd
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #include <asm/arch/cpu.h> /* get chip and board defs */
  17. #include <asm/arch/omap.h>
  18. /* Clock Defines */
  19. #define V_OSCK 26000000 /* Clock output from T2 */
  20. #define V_SCLK (V_OSCK >> 1)
  21. #define CONFIG_MISC_INIT_R
  22. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  23. #define CONFIG_SETUP_MEMORY_TAGS 1
  24. #define CONFIG_INITRD_TAG 1
  25. #define CONFIG_REVISION_TAG 1
  26. /*
  27. * Size of malloc() pool
  28. */
  29. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
  30. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  31. /* initial data */
  32. /*
  33. * DDR related
  34. */
  35. #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
  36. /*
  37. * Hardware drivers
  38. */
  39. /*
  40. * NS16550 Configuration
  41. */
  42. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  43. #define CONFIG_SYS_NS16550_SERIAL
  44. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  45. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  46. /*
  47. * select serial console configuration
  48. */
  49. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  50. #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
  51. /* allow to overwrite serial and ethaddr */
  52. #define CONFIG_ENV_OVERWRITE
  53. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  54. 115200}
  55. /*
  56. * USB configuration
  57. * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  58. * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  59. */
  60. #ifdef CONFIG_USB_AM35X
  61. #ifdef CONFIG_USB_MUSB_HCD
  62. #ifdef CONFIG_USB_KEYBOARD
  63. #define CONFIG_PREBOOT "usb start"
  64. #endif /* CONFIG_USB_KEYBOARD */
  65. #endif /* CONFIG_USB_MUSB_HCD */
  66. #ifdef CONFIG_USB_MUSB_UDC
  67. /* USB device configuration */
  68. #define CONFIG_USB_DEVICE 1
  69. #define CONFIG_USB_TTY 1
  70. /* Change these to suit your needs */
  71. #define CONFIG_USBD_VENDORID 0x0451
  72. #define CONFIG_USBD_PRODUCTID 0x5678
  73. #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
  74. #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
  75. #endif /* CONFIG_USB_MUSB_UDC */
  76. #endif /* CONFIG_USB_AM35X */
  77. #define CONFIG_SYS_I2C
  78. /*
  79. * Board NAND Info.
  80. */
  81. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  82. /* to access nand */
  83. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  84. /* to access */
  85. /* nand at CS0 */
  86. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  87. /* NAND devices */
  88. #define CONFIG_JFFS2_NAND
  89. /* nand device jffs2 lives on */
  90. #define CONFIG_JFFS2_DEV "nand0"
  91. /* start of jffs2 partition */
  92. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  93. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
  94. /* Environment information */
  95. #define CONFIG_BOOTFILE "uImage"
  96. #define CONFIG_EXTRA_ENV_SETTINGS \
  97. "loadaddr=0x82000000\0" \
  98. "console=ttyS2,115200n8\0" \
  99. "mmcdev=0\0" \
  100. "mmcargs=setenv bootargs console=${console} " \
  101. "root=/dev/mmcblk0p2 rw " \
  102. "rootfstype=ext3 rootwait\0" \
  103. "nandargs=setenv bootargs console=${console} " \
  104. "root=/dev/mtdblock4 rw " \
  105. "rootfstype=jffs2\0" \
  106. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  107. "bootscript=echo Running bootscript from mmc ...; " \
  108. "source ${loadaddr}\0" \
  109. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  110. "mmcboot=echo Booting from mmc ...; " \
  111. "run mmcargs; " \
  112. "bootm ${loadaddr}\0" \
  113. "nandboot=echo Booting from nand ...; " \
  114. "run nandargs; " \
  115. "nand read ${loadaddr} 280000 400000; " \
  116. "bootm ${loadaddr}\0" \
  117. #define CONFIG_BOOTCOMMAND \
  118. "mmc dev ${mmcdev}; if mmc rescan; then " \
  119. "if run loadbootscript; then " \
  120. "run bootscript; " \
  121. "else " \
  122. "if run loaduimage; then " \
  123. "run mmcboot; " \
  124. "else run nandboot; " \
  125. "fi; " \
  126. "fi; " \
  127. "else run nandboot; fi"
  128. /*
  129. * Miscellaneous configurable options
  130. */
  131. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  132. #define CONFIG_SYS_MAXARGS 32 /* max number of command */
  133. /* args */
  134. /* memtest works on */
  135. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  136. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  137. 0x01F00000) /* 31MB */
  138. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  139. /* address */
  140. /*
  141. * AM3517 has 12 GP timers, they can be driven by the system clock
  142. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  143. * This rate is divided by a local divisor.
  144. */
  145. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  146. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  147. /*-----------------------------------------------------------------------
  148. * Physical Memory Map
  149. */
  150. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  151. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  152. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  153. /*-----------------------------------------------------------------------
  154. * FLASH and environment organization
  155. */
  156. /* **** PISMO SUPPORT *** */
  157. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
  158. /* on one chip */
  159. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  160. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  161. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  162. /* Monitor at start of flash */
  163. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  164. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
  165. #define CONFIG_ENV_OFFSET 0x260000
  166. #define CONFIG_ENV_ADDR 0x260000
  167. /*-----------------------------------------------------------------------
  168. * CFI FLASH driver setup
  169. */
  170. /* timeout values are in ticks */
  171. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  172. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  173. /* Flash banks JFFS2 should use */
  174. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  175. CONFIG_SYS_MAX_NAND_DEVICE)
  176. #define CONFIG_SYS_JFFS2_MEM_NAND
  177. /* use flash_info[2] */
  178. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  179. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  180. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  181. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  182. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  183. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  184. CONFIG_SYS_INIT_RAM_SIZE - \
  185. GENERATED_GBL_DATA_SIZE)
  186. /* Defines for SPL */
  187. #define CONFIG_SPL_TEXT_BASE 0x40200800
  188. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  189. CONFIG_SPL_TEXT_BASE)
  190. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  191. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  192. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  193. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  194. #define CONFIG_SPL_NAND_BASE
  195. #define CONFIG_SPL_NAND_DRIVERS
  196. #define CONFIG_SPL_NAND_ECC
  197. /* NAND boot config */
  198. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  199. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  200. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  201. #define CONFIG_SYS_NAND_OOBSIZE 64
  202. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  203. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  204. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  205. 10, 11, 12, 13}
  206. #define CONFIG_SYS_NAND_ECCSIZE 512
  207. #define CONFIG_SYS_NAND_ECCBYTES 3
  208. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  209. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  210. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  211. /*
  212. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  213. * 64 bytes before this address should be set aside for u-boot.img's
  214. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  215. * other needs.
  216. */
  217. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  218. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  219. #endif /* __CONFIG_H */