T208xQDS.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T2080/T2081 QDS board configuration file
  7. */
  8. #ifndef __T208xQDS_H
  9. #define __T208xQDS_H
  10. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  11. #if defined(CONFIG_ARCH_T2080)
  12. #define CONFIG_FSL_SATA_V2
  13. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  14. #define CONFIG_SRIO1 /* SRIO port 1 */
  15. #define CONFIG_SRIO2 /* SRIO port 2 */
  16. #elif defined(CONFIG_ARCH_T2081)
  17. #endif
  18. /* High Level Configuration Options */
  19. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  20. #define CONFIG_MP /* support multiple processors */
  21. #define CONFIG_ENABLE_36BIT_PHYS
  22. #ifdef CONFIG_PHYS_64BIT
  23. #define CONFIG_ADDR_MAP 1
  24. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  25. #endif
  26. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  27. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  28. #define CONFIG_ENV_OVERWRITE
  29. #ifdef CONFIG_RAMBOOT_PBL
  30. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  31. #define CONFIG_SPL_FLUSH_IMAGE
  32. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  33. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  34. #define CONFIG_SPL_PAD_TO 0x40000
  35. #define CONFIG_SPL_MAX_SIZE 0x28000
  36. #define RESET_VECTOR_OFFSET 0x27FFC
  37. #define BOOT_PAGE_OFFSET 0x27000
  38. #ifdef CONFIG_SPL_BUILD
  39. #define CONFIG_SPL_SKIP_RELOCATE
  40. #define CONFIG_SPL_COMMON_INIT_DDR
  41. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  42. #endif
  43. #ifdef CONFIG_NAND
  44. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  45. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  46. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  47. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  48. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  49. #if defined(CONFIG_ARCH_T2080)
  50. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  51. #elif defined(CONFIG_ARCH_T2081)
  52. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  53. #endif
  54. #define CONFIG_SPL_NAND_BOOT
  55. #endif
  56. #ifdef CONFIG_SPIFLASH
  57. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  58. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  59. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  60. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  61. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  62. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  63. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  64. #ifndef CONFIG_SPL_BUILD
  65. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66. #endif
  67. #if defined(CONFIG_ARCH_T2080)
  68. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  69. #elif defined(CONFIG_ARCH_T2081)
  70. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  71. #endif
  72. #define CONFIG_SPL_SPI_BOOT
  73. #endif
  74. #ifdef CONFIG_SDCARD
  75. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  76. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  77. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  78. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  79. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  80. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81. #ifndef CONFIG_SPL_BUILD
  82. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83. #endif
  84. #if defined(CONFIG_ARCH_T2080)
  85. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  86. #elif defined(CONFIG_ARCH_T2081)
  87. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  88. #endif
  89. #define CONFIG_SPL_MMC_BOOT
  90. #endif
  91. #endif /* CONFIG_RAMBOOT_PBL */
  92. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  93. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  94. /* Set 1M boot space */
  95. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  96. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  97. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  98. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  99. #endif
  100. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  101. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  102. #endif
  103. /*
  104. * These can be toggled for performance analysis, otherwise use default.
  105. */
  106. #define CONFIG_SYS_CACHE_STASHING
  107. #define CONFIG_BTB /* toggle branch predition */
  108. #define CONFIG_DDR_ECC
  109. #ifdef CONFIG_DDR_ECC
  110. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  111. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  112. #endif
  113. #ifdef CONFIG_MTD_NOR_FLASH
  114. #define CONFIG_FLASH_CFI_DRIVER
  115. #define CONFIG_SYS_FLASH_CFI
  116. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  117. #endif
  118. #if defined(CONFIG_SPIFLASH)
  119. #define CONFIG_SYS_EXTRA_ENV_RELOC
  120. #define CONFIG_ENV_SPI_BUS 0
  121. #define CONFIG_ENV_SPI_CS 0
  122. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  123. #define CONFIG_ENV_SPI_MODE 0
  124. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  125. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  126. #define CONFIG_ENV_SECT_SIZE 0x10000
  127. #elif defined(CONFIG_SDCARD)
  128. #define CONFIG_SYS_EXTRA_ENV_RELOC
  129. #define CONFIG_SYS_MMC_ENV_DEV 0
  130. #define CONFIG_ENV_SIZE 0x2000
  131. #define CONFIG_ENV_OFFSET (512 * 0x800)
  132. #elif defined(CONFIG_NAND)
  133. #define CONFIG_SYS_EXTRA_ENV_RELOC
  134. #define CONFIG_ENV_SIZE 0x2000
  135. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  136. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  137. #define CONFIG_ENV_ADDR 0xffe20000
  138. #define CONFIG_ENV_SIZE 0x2000
  139. #elif defined(CONFIG_ENV_IS_NOWHERE)
  140. #define CONFIG_ENV_SIZE 0x2000
  141. #else
  142. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  143. #define CONFIG_ENV_SIZE 0x2000
  144. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  145. #endif
  146. #ifndef __ASSEMBLY__
  147. unsigned long get_board_sys_clk(void);
  148. unsigned long get_board_ddr_clk(void);
  149. #endif
  150. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  151. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  152. /*
  153. * Config the L3 Cache as L3 SRAM
  154. */
  155. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  156. #define CONFIG_SYS_L3_SIZE (512 << 10)
  157. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  158. #ifdef CONFIG_RAMBOOT_PBL
  159. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  160. #endif
  161. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  162. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  163. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  164. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  165. #define CONFIG_SYS_DCSRBAR 0xf0000000
  166. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  167. /* EEPROM */
  168. #define CONFIG_ID_EEPROM
  169. #define CONFIG_SYS_I2C_EEPROM_NXID
  170. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  171. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  172. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  173. /*
  174. * DDR Setup
  175. */
  176. #define CONFIG_VERY_BIG_RAM
  177. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  178. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  179. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  180. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  181. #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  182. #define CONFIG_DDR_SPD
  183. #define CONFIG_FSL_DDR_INTERACTIVE
  184. #define CONFIG_SYS_SPD_BUS_NUM 0
  185. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  186. #define SPD_EEPROM_ADDRESS1 0x51
  187. #define SPD_EEPROM_ADDRESS2 0x52
  188. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  189. #define CTRL_INTLV_PREFERED cacheline
  190. /*
  191. * IFC Definitions
  192. */
  193. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  194. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  195. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  196. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  197. + 0x8000000) | \
  198. CSPR_PORT_SIZE_16 | \
  199. CSPR_MSEL_NOR | \
  200. CSPR_V)
  201. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  202. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  203. CSPR_PORT_SIZE_16 | \
  204. CSPR_MSEL_NOR | \
  205. CSPR_V)
  206. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  207. /* NOR Flash Timing Params */
  208. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  209. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  210. FTIM0_NOR_TEADC(0x5) | \
  211. FTIM0_NOR_TEAHC(0x5))
  212. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  213. FTIM1_NOR_TRAD_NOR(0x1A) |\
  214. FTIM1_NOR_TSEQRAD_NOR(0x13))
  215. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  216. FTIM2_NOR_TCH(0x4) | \
  217. FTIM2_NOR_TWPH(0x0E) | \
  218. FTIM2_NOR_TWP(0x1c))
  219. #define CONFIG_SYS_NOR_FTIM3 0x0
  220. #define CONFIG_SYS_FLASH_QUIET_TEST
  221. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  222. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  223. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  224. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  225. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  226. #define CONFIG_SYS_FLASH_EMPTY_INFO
  227. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  228. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  229. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  230. #define QIXIS_BASE 0xffdf0000
  231. #define QIXIS_LBMAP_SWITCH 6
  232. #define QIXIS_LBMAP_MASK 0x0f
  233. #define QIXIS_LBMAP_SHIFT 0
  234. #define QIXIS_LBMAP_DFLTBANK 0x00
  235. #define QIXIS_LBMAP_ALTBANK 0x04
  236. #define QIXIS_LBMAP_NAND 0x09
  237. #define QIXIS_LBMAP_SD 0x00
  238. #define QIXIS_RCW_SRC_NAND 0x104
  239. #define QIXIS_RCW_SRC_SD 0x040
  240. #define QIXIS_RST_CTL_RESET 0x83
  241. #define QIXIS_RST_FORCE_MEM 0x1
  242. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  243. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  244. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  245. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  246. #define CONFIG_SYS_CSPR3_EXT (0xf)
  247. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  248. | CSPR_PORT_SIZE_8 \
  249. | CSPR_MSEL_GPCM \
  250. | CSPR_V)
  251. #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
  252. #define CONFIG_SYS_CSOR3 0x0
  253. /* QIXIS Timing parameters for IFC CS3 */
  254. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  255. FTIM0_GPCM_TEADC(0x0e) | \
  256. FTIM0_GPCM_TEAHC(0x0e))
  257. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  258. FTIM1_GPCM_TRAD(0x3f))
  259. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  260. FTIM2_GPCM_TCH(0x8) | \
  261. FTIM2_GPCM_TWP(0x1f))
  262. #define CONFIG_SYS_CS3_FTIM3 0x0
  263. /* NAND Flash on IFC */
  264. #define CONFIG_NAND_FSL_IFC
  265. #define CONFIG_SYS_NAND_BASE 0xff800000
  266. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  267. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  268. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  269. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  270. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  271. | CSPR_V)
  272. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  273. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  274. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  275. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  276. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  277. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  278. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  279. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  280. #define CONFIG_SYS_NAND_ONFI_DETECTION
  281. /* ONFI NAND Flash mode0 Timing Params */
  282. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  283. FTIM0_NAND_TWP(0x18) | \
  284. FTIM0_NAND_TWCHT(0x07) | \
  285. FTIM0_NAND_TWH(0x0a))
  286. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  287. FTIM1_NAND_TWBE(0x39) | \
  288. FTIM1_NAND_TRR(0x0e) | \
  289. FTIM1_NAND_TRP(0x18))
  290. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  291. FTIM2_NAND_TREH(0x0a) | \
  292. FTIM2_NAND_TWHRE(0x1e))
  293. #define CONFIG_SYS_NAND_FTIM3 0x0
  294. #define CONFIG_SYS_NAND_DDR_LAW 11
  295. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  296. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  297. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  298. #if defined(CONFIG_NAND)
  299. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  300. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  301. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  302. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  303. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  304. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  305. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  306. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  307. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  308. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  309. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  310. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  311. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  312. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  313. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  314. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  315. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  316. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  317. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  318. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  319. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  320. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  321. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  322. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  323. #else
  324. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  325. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  326. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  327. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  328. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  329. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  330. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  331. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  332. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  333. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  334. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  335. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  336. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  337. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  338. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  339. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  340. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  341. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  342. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  343. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  344. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  345. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  346. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  347. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  348. #endif
  349. #if defined(CONFIG_RAMBOOT_PBL)
  350. #define CONFIG_SYS_RAMBOOT
  351. #endif
  352. #ifdef CONFIG_SPL_BUILD
  353. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  354. #else
  355. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  356. #endif
  357. #define CONFIG_MISC_INIT_R
  358. #define CONFIG_HWCONFIG
  359. /* define to use L1 as initial stack */
  360. #define CONFIG_L1_INIT_RAM
  361. #define CONFIG_SYS_INIT_RAM_LOCK
  362. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  363. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  364. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  365. /* The assembler doesn't like typecast */
  366. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  367. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  368. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  369. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  370. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  371. GENERATED_GBL_DATA_SIZE)
  372. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  373. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  374. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  375. /*
  376. * Serial Port
  377. */
  378. #define CONFIG_SYS_NS16550_SERIAL
  379. #define CONFIG_SYS_NS16550_REG_SIZE 1
  380. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  381. #define CONFIG_SYS_BAUDRATE_TABLE \
  382. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  383. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  384. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  385. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  386. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  387. /*
  388. * I2C
  389. */
  390. #define CONFIG_SYS_I2C
  391. #define CONFIG_SYS_I2C_FSL
  392. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  393. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  394. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  395. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  396. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  397. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  398. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  399. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  400. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  401. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  402. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  403. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  404. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  405. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  406. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  407. #define I2C_MUX_CH_DEFAULT 0x8
  408. #define I2C_MUX_CH_VOL_MONITOR 0xa
  409. /* Voltage monitor on channel 2*/
  410. #define I2C_VOL_MONITOR_ADDR 0x40
  411. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  412. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  413. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  414. #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
  415. #ifndef CONFIG_SPL_BUILD
  416. #define CONFIG_VID
  417. #endif
  418. #define CONFIG_VOL_MONITOR_IR36021_SET
  419. #define CONFIG_VOL_MONITOR_IR36021_READ
  420. /* The lowest and highest voltage allowed for T208xQDS */
  421. #define VDD_MV_MIN 819
  422. #define VDD_MV_MAX 1212
  423. /*
  424. * RapidIO
  425. */
  426. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  427. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  428. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  429. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  430. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  431. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  432. /*
  433. * for slave u-boot IMAGE instored in master memory space,
  434. * PHYS must be aligned based on the SIZE
  435. */
  436. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  437. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  438. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  439. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  440. /*
  441. * for slave UCODE and ENV instored in master memory space,
  442. * PHYS must be aligned based on the SIZE
  443. */
  444. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  445. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  446. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  447. /* slave core release by master*/
  448. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  449. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  450. /*
  451. * SRIO_PCIE_BOOT - SLAVE
  452. */
  453. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  454. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  455. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  456. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  457. #endif
  458. /*
  459. * eSPI - Enhanced SPI
  460. */
  461. #ifdef CONFIG_SPI_FLASH
  462. #ifndef CONFIG_SPL_BUILD
  463. #endif
  464. #define CONFIG_SPI_FLASH_BAR
  465. #define CONFIG_SF_DEFAULT_SPEED 10000000
  466. #define CONFIG_SF_DEFAULT_MODE 0
  467. #endif
  468. /*
  469. * General PCI
  470. * Memory space is mapped 1-1, but I/O space must start from 0.
  471. */
  472. #define CONFIG_PCIE1 /* PCIE controller 1 */
  473. #define CONFIG_PCIE2 /* PCIE controller 2 */
  474. #define CONFIG_PCIE3 /* PCIE controller 3 */
  475. #define CONFIG_PCIE4 /* PCIE controller 4 */
  476. #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
  477. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  478. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  479. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  480. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  481. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  482. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  483. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  484. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  485. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  486. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  487. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  488. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  489. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  490. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  491. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  492. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  493. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  494. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  495. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  496. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  497. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  498. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  499. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  500. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  501. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  502. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  503. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  504. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  505. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  506. /* controller 4, Base address 203000 */
  507. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  508. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  509. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  510. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  511. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  512. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  513. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  514. #ifdef CONFIG_PCI
  515. #define CONFIG_PCI_INDIRECT_BRIDGE
  516. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  517. #endif
  518. /* Qman/Bman */
  519. #ifndef CONFIG_NOBQFMAN
  520. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  521. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  522. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  523. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  524. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  525. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  526. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  527. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  528. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  529. CONFIG_SYS_BMAN_CENA_SIZE)
  530. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  531. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  532. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  533. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  534. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  535. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  536. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  537. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  538. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  539. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  540. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  541. CONFIG_SYS_QMAN_CENA_SIZE)
  542. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  543. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  544. #define CONFIG_SYS_DPAA_FMAN
  545. #define CONFIG_SYS_DPAA_PME
  546. #define CONFIG_SYS_PMAN
  547. #define CONFIG_SYS_DPAA_DCE
  548. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  549. #define CONFIG_SYS_INTERLAKEN
  550. /* Default address of microcode for the Linux Fman driver */
  551. #if defined(CONFIG_SPIFLASH)
  552. /*
  553. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  554. * env, so we got 0x110000.
  555. */
  556. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  557. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  558. #elif defined(CONFIG_SDCARD)
  559. /*
  560. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  561. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  562. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  563. */
  564. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  565. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  566. #elif defined(CONFIG_NAND)
  567. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  568. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  569. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  570. /*
  571. * Slave has no ucode locally, it can fetch this from remote. When implementing
  572. * in two corenet boards, slave's ucode could be stored in master's memory
  573. * space, the address can be mapped from slave TLB->slave LAW->
  574. * slave SRIO or PCIE outbound window->master inbound window->
  575. * master LAW->the ucode address in master's memory space.
  576. */
  577. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  578. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  579. #else
  580. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  581. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  582. #endif
  583. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  584. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  585. #endif /* CONFIG_NOBQFMAN */
  586. #ifdef CONFIG_SYS_DPAA_FMAN
  587. #define CONFIG_FMAN_ENET
  588. #define CONFIG_PHYLIB_10G
  589. #define CONFIG_PHY_VITESSE
  590. #define CONFIG_PHY_REALTEK
  591. #define CONFIG_PHY_TERANETICS
  592. #define RGMII_PHY1_ADDR 0x1
  593. #define RGMII_PHY2_ADDR 0x2
  594. #define FM1_10GEC1_PHY_ADDR 0x3
  595. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  596. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  597. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  598. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  599. #endif
  600. #ifdef CONFIG_FMAN_ENET
  601. #define CONFIG_MII /* MII PHY management */
  602. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  603. #endif
  604. /*
  605. * SATA
  606. */
  607. #ifdef CONFIG_FSL_SATA_V2
  608. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  609. #define CONFIG_SATA1
  610. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  611. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  612. #define CONFIG_SATA2
  613. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  614. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  615. #define CONFIG_LBA48
  616. #endif
  617. /*
  618. * USB
  619. */
  620. #ifdef CONFIG_USB_EHCI_HCD
  621. #define CONFIG_USB_EHCI_FSL
  622. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  623. #define CONFIG_HAS_FSL_DR_USB
  624. #endif
  625. /*
  626. * SDHC
  627. */
  628. #ifdef CONFIG_MMC
  629. #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  630. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  631. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  632. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  633. #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
  634. #endif
  635. /*
  636. * Dynamic MTD Partition support with mtdparts
  637. */
  638. #ifdef CONFIG_MTD_NOR_FLASH
  639. #define CONFIG_MTD_DEVICE
  640. #define CONFIG_MTD_PARTITIONS
  641. #define CONFIG_FLASH_CFI_MTD
  642. #endif
  643. /*
  644. * Environment
  645. */
  646. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  647. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  648. /*
  649. * Miscellaneous configurable options
  650. */
  651. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  652. /*
  653. * For booting Linux, the board info and command line data
  654. * have to be in the first 64 MB of memory, since this is
  655. * the maximum mapped by the Linux kernel during initialization.
  656. */
  657. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  658. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  659. #ifdef CONFIG_CMD_KGDB
  660. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  661. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  662. #endif
  663. /*
  664. * Environment Configuration
  665. */
  666. #define CONFIG_ROOTPATH "/opt/nfsroot"
  667. #define CONFIG_BOOTFILE "uImage"
  668. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  669. /* default location for tftp and bootm */
  670. #define CONFIG_LOADADDR 1000000
  671. #define __USB_PHY_TYPE utmi
  672. #define CONFIG_EXTRA_ENV_SETTINGS \
  673. "hwconfig=fsl_ddr:" \
  674. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  675. "bank_intlv=auto;" \
  676. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  677. "netdev=eth0\0" \
  678. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  679. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  680. "tftpflash=tftpboot $loadaddr $uboot && " \
  681. "protect off $ubootaddr +$filesize && " \
  682. "erase $ubootaddr +$filesize && " \
  683. "cp.b $loadaddr $ubootaddr $filesize && " \
  684. "protect on $ubootaddr +$filesize && " \
  685. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  686. "consoledev=ttyS0\0" \
  687. "ramdiskaddr=2000000\0" \
  688. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  689. "fdtaddr=1e00000\0" \
  690. "fdtfile=t2080qds/t2080qds.dtb\0" \
  691. "bdev=sda3\0"
  692. /*
  693. * For emulation this causes u-boot to jump to the start of the
  694. * proof point app code automatically
  695. */
  696. #define CONFIG_PROOF_POINTS \
  697. "setenv bootargs root=/dev/$bdev rw " \
  698. "console=$consoledev,$baudrate $othbootargs;" \
  699. "cpu 1 release 0x29000000 - - -;" \
  700. "cpu 2 release 0x29000000 - - -;" \
  701. "cpu 3 release 0x29000000 - - -;" \
  702. "cpu 4 release 0x29000000 - - -;" \
  703. "cpu 5 release 0x29000000 - - -;" \
  704. "cpu 6 release 0x29000000 - - -;" \
  705. "cpu 7 release 0x29000000 - - -;" \
  706. "go 0x29000000"
  707. #define CONFIG_HVBOOT \
  708. "setenv bootargs config-addr=0x60000000; " \
  709. "bootm 0x01000000 - 0x00f00000"
  710. #define CONFIG_ALU \
  711. "setenv bootargs root=/dev/$bdev rw " \
  712. "console=$consoledev,$baudrate $othbootargs;" \
  713. "cpu 1 release 0x01000000 - - -;" \
  714. "cpu 2 release 0x01000000 - - -;" \
  715. "cpu 3 release 0x01000000 - - -;" \
  716. "cpu 4 release 0x01000000 - - -;" \
  717. "cpu 5 release 0x01000000 - - -;" \
  718. "cpu 6 release 0x01000000 - - -;" \
  719. "cpu 7 release 0x01000000 - - -;" \
  720. "go 0x01000000"
  721. #define CONFIG_LINUX \
  722. "setenv bootargs root=/dev/ram rw " \
  723. "console=$consoledev,$baudrate $othbootargs;" \
  724. "setenv ramdiskaddr 0x02000000;" \
  725. "setenv fdtaddr 0x00c00000;" \
  726. "setenv loadaddr 0x1000000;" \
  727. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  728. #define CONFIG_HDBOOT \
  729. "setenv bootargs root=/dev/$bdev rw " \
  730. "console=$consoledev,$baudrate $othbootargs;" \
  731. "tftp $loadaddr $bootfile;" \
  732. "tftp $fdtaddr $fdtfile;" \
  733. "bootm $loadaddr - $fdtaddr"
  734. #define CONFIG_NFSBOOTCOMMAND \
  735. "setenv bootargs root=/dev/nfs rw " \
  736. "nfsroot=$serverip:$rootpath " \
  737. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  738. "console=$consoledev,$baudrate $othbootargs;" \
  739. "tftp $loadaddr $bootfile;" \
  740. "tftp $fdtaddr $fdtfile;" \
  741. "bootm $loadaddr - $fdtaddr"
  742. #define CONFIG_RAMBOOTCOMMAND \
  743. "setenv bootargs root=/dev/ram rw " \
  744. "console=$consoledev,$baudrate $othbootargs;" \
  745. "tftp $ramdiskaddr $ramdiskfile;" \
  746. "tftp $loadaddr $bootfile;" \
  747. "tftp $fdtaddr $fdtfile;" \
  748. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  749. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  750. #include <asm/fsl_secure_boot.h>
  751. #endif /* __T208xQDS_H */