T1040QDS.h 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714
  1. /*
  2. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. /*
  25. * T1040 QDS board configuration file
  26. */
  27. #ifdef CONFIG_RAMBOOT_PBL
  28. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  29. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  30. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  31. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  32. #endif
  33. /* High Level Configuration Options */
  34. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  35. #define CONFIG_MP /* support multiple processors */
  36. /* support deep sleep */
  37. #define CONFIG_DEEP_SLEEP
  38. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  39. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  40. #endif
  41. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  42. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  43. #define CONFIG_PCI_INDIRECT_BRIDGE
  44. #define CONFIG_PCIE1 /* PCIE controller 1 */
  45. #define CONFIG_PCIE2 /* PCIE controller 2 */
  46. #define CONFIG_PCIE3 /* PCIE controller 3 */
  47. #define CONFIG_PCIE4 /* PCIE controller 4 */
  48. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  49. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  50. #define CONFIG_ENV_OVERWRITE
  51. #ifndef CONFIG_MTD_NOR_FLASH
  52. #else
  53. #define CONFIG_FLASH_CFI_DRIVER
  54. #define CONFIG_SYS_FLASH_CFI
  55. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  56. #endif
  57. #ifdef CONFIG_MTD_NOR_FLASH
  58. #if defined(CONFIG_SPIFLASH)
  59. #define CONFIG_SYS_EXTRA_ENV_RELOC
  60. #define CONFIG_ENV_SPI_BUS 0
  61. #define CONFIG_ENV_SPI_CS 0
  62. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  63. #define CONFIG_ENV_SPI_MODE 0
  64. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  65. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  66. #define CONFIG_ENV_SECT_SIZE 0x10000
  67. #elif defined(CONFIG_SDCARD)
  68. #define CONFIG_SYS_EXTRA_ENV_RELOC
  69. #define CONFIG_SYS_MMC_ENV_DEV 0
  70. #define CONFIG_ENV_SIZE 0x2000
  71. #define CONFIG_ENV_OFFSET (512 * 1658)
  72. #elif defined(CONFIG_NAND)
  73. #define CONFIG_SYS_EXTRA_ENV_RELOC
  74. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  75. #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  76. #else
  77. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  78. #define CONFIG_ENV_SIZE 0x2000
  79. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  80. #endif
  81. #else /* CONFIG_MTD_NOR_FLASH */
  82. #define CONFIG_ENV_SIZE 0x2000
  83. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  84. #endif
  85. #ifndef __ASSEMBLY__
  86. unsigned long get_board_sys_clk(void);
  87. unsigned long get_board_ddr_clk(void);
  88. #endif
  89. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  90. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  91. /*
  92. * These can be toggled for performance analysis, otherwise use default.
  93. */
  94. #define CONFIG_SYS_CACHE_STASHING
  95. #define CONFIG_BACKSIDE_L2_CACHE
  96. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  97. #define CONFIG_BTB /* toggle branch predition */
  98. #define CONFIG_DDR_ECC
  99. #ifdef CONFIG_DDR_ECC
  100. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  101. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  102. #endif
  103. #define CONFIG_ENABLE_36BIT_PHYS
  104. #define CONFIG_ADDR_MAP
  105. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  106. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  107. #define CONFIG_SYS_MEMTEST_END 0x00400000
  108. /*
  109. * Config the L3 Cache as L3 SRAM
  110. */
  111. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  112. #define CONFIG_SYS_DCSRBAR 0xf0000000
  113. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  114. /* EEPROM */
  115. #define CONFIG_ID_EEPROM
  116. #define CONFIG_SYS_I2C_EEPROM_NXID
  117. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  118. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  119. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  120. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  121. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  122. /*
  123. * DDR Setup
  124. */
  125. #define CONFIG_VERY_BIG_RAM
  126. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  127. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  128. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  129. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  130. #define CONFIG_DDR_SPD
  131. #define CONFIG_FSL_DDR_INTERACTIVE
  132. #define CONFIG_SYS_SPD_BUS_NUM 0
  133. #define SPD_EEPROM_ADDRESS 0x51
  134. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  135. /*
  136. * IFC Definitions
  137. */
  138. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  139. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  140. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  141. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  142. + 0x8000000) | \
  143. CSPR_PORT_SIZE_16 | \
  144. CSPR_MSEL_NOR | \
  145. CSPR_V)
  146. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  147. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  148. CSPR_PORT_SIZE_16 | \
  149. CSPR_MSEL_NOR | \
  150. CSPR_V)
  151. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  152. /*
  153. * TDM Definition
  154. */
  155. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  156. /* NOR Flash Timing Params */
  157. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  158. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  159. FTIM0_NOR_TEADC(0x5) | \
  160. FTIM0_NOR_TEAHC(0x5))
  161. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  162. FTIM1_NOR_TRAD_NOR(0x1A) |\
  163. FTIM1_NOR_TSEQRAD_NOR(0x13))
  164. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  165. FTIM2_NOR_TCH(0x4) | \
  166. FTIM2_NOR_TWPH(0x0E) | \
  167. FTIM2_NOR_TWP(0x1c))
  168. #define CONFIG_SYS_NOR_FTIM3 0x0
  169. #define CONFIG_SYS_FLASH_QUIET_TEST
  170. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  171. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  172. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  173. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  174. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  175. #define CONFIG_SYS_FLASH_EMPTY_INFO
  176. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  177. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  178. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  179. #define QIXIS_BASE 0xffdf0000
  180. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  181. #define QIXIS_LBMAP_SWITCH 0x06
  182. #define QIXIS_LBMAP_MASK 0x0f
  183. #define QIXIS_LBMAP_SHIFT 0
  184. #define QIXIS_LBMAP_DFLTBANK 0x00
  185. #define QIXIS_LBMAP_ALTBANK 0x04
  186. #define QIXIS_RST_CTL_RESET 0x31
  187. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  188. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  189. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  190. #define QIXIS_RST_FORCE_MEM 0x01
  191. #define CONFIG_SYS_CSPR3_EXT (0xf)
  192. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  193. | CSPR_PORT_SIZE_8 \
  194. | CSPR_MSEL_GPCM \
  195. | CSPR_V)
  196. #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
  197. #define CONFIG_SYS_CSOR3 0x0
  198. /* QIXIS Timing parameters for IFC CS3 */
  199. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  200. FTIM0_GPCM_TEADC(0x0e) | \
  201. FTIM0_GPCM_TEAHC(0x0e))
  202. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  203. FTIM1_GPCM_TRAD(0x3f))
  204. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  205. FTIM2_GPCM_TCH(0x8) | \
  206. FTIM2_GPCM_TWP(0x1f))
  207. #define CONFIG_SYS_CS3_FTIM3 0x0
  208. #define CONFIG_NAND_FSL_IFC
  209. #define CONFIG_SYS_NAND_BASE 0xff800000
  210. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  211. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  212. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  213. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  214. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  215. | CSPR_V)
  216. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  217. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  218. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  219. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  220. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  221. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  222. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  223. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  224. #define CONFIG_SYS_NAND_ONFI_DETECTION
  225. /* ONFI NAND Flash mode0 Timing Params */
  226. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  227. FTIM0_NAND_TWP(0x18) | \
  228. FTIM0_NAND_TWCHT(0x07) | \
  229. FTIM0_NAND_TWH(0x0a))
  230. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  231. FTIM1_NAND_TWBE(0x39) | \
  232. FTIM1_NAND_TRR(0x0e) | \
  233. FTIM1_NAND_TRP(0x18))
  234. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  235. FTIM2_NAND_TREH(0x0a) | \
  236. FTIM2_NAND_TWHRE(0x1e))
  237. #define CONFIG_SYS_NAND_FTIM3 0x0
  238. #define CONFIG_SYS_NAND_DDR_LAW 11
  239. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  240. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  241. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  242. #if defined(CONFIG_NAND)
  243. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  244. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  245. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  246. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  247. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  248. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  249. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  250. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  251. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  252. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  253. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  254. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  255. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  256. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  257. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  258. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  259. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  260. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  261. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  262. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  263. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  264. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  265. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  266. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  267. #else
  268. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  269. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  270. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  271. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  272. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  273. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  274. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  275. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  276. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  277. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  278. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  279. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  280. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  281. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  282. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  283. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  284. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  285. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  286. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  287. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  288. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  289. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  290. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  291. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  292. #endif
  293. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  294. #if defined(CONFIG_RAMBOOT_PBL)
  295. #define CONFIG_SYS_RAMBOOT
  296. #endif
  297. #define CONFIG_MISC_INIT_R
  298. #define CONFIG_HWCONFIG
  299. /* define to use L1 as initial stack */
  300. #define CONFIG_L1_INIT_RAM
  301. #define CONFIG_SYS_INIT_RAM_LOCK
  302. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  303. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  304. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  305. /* The assembler doesn't like typecast */
  306. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  307. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  308. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  309. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  310. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  311. GENERATED_GBL_DATA_SIZE)
  312. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  313. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  314. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  315. /* Serial Port - controlled on board with jumper J8
  316. * open - index 2
  317. * shorted - index 1
  318. */
  319. #define CONFIG_SYS_NS16550_SERIAL
  320. #define CONFIG_SYS_NS16550_REG_SIZE 1
  321. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  322. #define CONFIG_SYS_BAUDRATE_TABLE \
  323. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  324. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  325. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  326. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  327. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  328. /* Video */
  329. #define CONFIG_FSL_DIU_FB
  330. #ifdef CONFIG_FSL_DIU_FB
  331. #define CONFIG_FSL_DIU_CH7301
  332. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  333. #define CONFIG_VIDEO_LOGO
  334. #define CONFIG_VIDEO_BMP_LOGO
  335. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  336. /*
  337. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  338. * disable empty flash sector detection, which is I/O-intensive.
  339. */
  340. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  341. #endif
  342. /* I2C */
  343. #define CONFIG_SYS_I2C
  344. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  345. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  346. #define CONFIG_SYS_FSL_I2C2_SPEED 50000
  347. #define CONFIG_SYS_FSL_I2C3_SPEED 50000
  348. #define CONFIG_SYS_FSL_I2C4_SPEED 50000
  349. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  350. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  351. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  352. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  353. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  354. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  355. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  356. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  357. #define I2C_MUX_PCA_ADDR 0x77
  358. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  359. /* I2C bus multiplexer */
  360. #define I2C_MUX_CH_DEFAULT 0x8
  361. #define I2C_MUX_CH_DIU 0xC
  362. /* LDI/DVI Encoder for display */
  363. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  364. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  365. /*
  366. * RTC configuration
  367. */
  368. #define RTC
  369. #define CONFIG_RTC_DS3231 1
  370. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  371. /*
  372. * eSPI - Enhanced SPI
  373. */
  374. #define CONFIG_SF_DEFAULT_SPEED 10000000
  375. #define CONFIG_SF_DEFAULT_MODE 0
  376. /*
  377. * General PCI
  378. * Memory space is mapped 1-1, but I/O space must start from 0.
  379. */
  380. #ifdef CONFIG_PCI
  381. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  382. #ifdef CONFIG_PCIE1
  383. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  384. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  385. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  386. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  387. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  388. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  389. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  390. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  391. #endif
  392. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  393. #ifdef CONFIG_PCIE2
  394. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  395. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  396. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  397. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  398. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  399. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  400. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  401. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  402. #endif
  403. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  404. #ifdef CONFIG_PCIE3
  405. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  406. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  407. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  408. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  409. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  410. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  411. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  412. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  413. #endif
  414. /* controller 4, Base address 203000 */
  415. #ifdef CONFIG_PCIE4
  416. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  417. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  418. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  419. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  420. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  421. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  422. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  423. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  424. #endif
  425. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  426. #endif /* CONFIG_PCI */
  427. /* SATA */
  428. #define CONFIG_FSL_SATA_V2
  429. #ifdef CONFIG_FSL_SATA_V2
  430. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  431. #define CONFIG_SATA1
  432. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  433. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  434. #define CONFIG_SATA2
  435. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  436. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  437. #define CONFIG_LBA48
  438. #endif
  439. /*
  440. * USB
  441. */
  442. #define CONFIG_HAS_FSL_DR_USB
  443. #ifdef CONFIG_HAS_FSL_DR_USB
  444. #ifdef CONFIG_USB_EHCI_HCD
  445. #define CONFIG_USB_EHCI_FSL
  446. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  447. #endif
  448. #endif
  449. #ifdef CONFIG_MMC
  450. #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  451. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  452. #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
  453. #endif
  454. /* Qman/Bman */
  455. #ifndef CONFIG_NOBQFMAN
  456. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  457. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  458. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  459. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  460. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  461. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  462. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  463. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  464. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  465. CONFIG_SYS_BMAN_CENA_SIZE)
  466. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  467. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  468. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  469. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  470. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  471. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  472. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  473. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  474. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  475. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  476. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  477. CONFIG_SYS_QMAN_CENA_SIZE)
  478. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  479. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  480. #define CONFIG_SYS_DPAA_FMAN
  481. #define CONFIG_SYS_DPAA_PME
  482. #define CONFIG_QE
  483. #define CONFIG_U_QE
  484. /* Default address of microcode for the Linux Fman driver */
  485. #if defined(CONFIG_SPIFLASH)
  486. /*
  487. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  488. * env, so we got 0x110000.
  489. */
  490. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  491. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  492. #elif defined(CONFIG_SDCARD)
  493. /*
  494. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  495. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  496. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  497. */
  498. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  499. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  500. #elif defined(CONFIG_NAND)
  501. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  502. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  503. #else
  504. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  505. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  506. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  507. #endif
  508. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  509. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  510. #endif /* CONFIG_NOBQFMAN */
  511. #ifdef CONFIG_SYS_DPAA_FMAN
  512. #define CONFIG_FMAN_ENET
  513. #define CONFIG_PHYLIB_10G
  514. #define CONFIG_PHY_VITESSE
  515. #define CONFIG_PHY_REALTEK
  516. #define CONFIG_PHY_TERANETICS
  517. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  518. #define SGMII_CARD_PORT2_PHY_ADDR 0x10
  519. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  520. #define SGMII_CARD_PORT4_PHY_ADDR 0x11
  521. #endif
  522. #ifdef CONFIG_FMAN_ENET
  523. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
  524. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
  525. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  526. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  527. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  528. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  529. #define CONFIG_MII /* MII PHY management */
  530. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  531. #endif
  532. /* Enable VSC9953 L2 Switch driver */
  533. #define CONFIG_VSC9953
  534. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
  535. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
  536. /*
  537. * Dynamic MTD Partition support with mtdparts
  538. */
  539. #ifdef CONFIG_MTD_NOR_FLASH
  540. #define CONFIG_MTD_DEVICE
  541. #define CONFIG_MTD_PARTITIONS
  542. #define CONFIG_FLASH_CFI_MTD
  543. #endif
  544. /*
  545. * Environment
  546. */
  547. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  548. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  549. /*
  550. * Miscellaneous configurable options
  551. */
  552. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  553. /*
  554. * For booting Linux, the board info and command line data
  555. * have to be in the first 64 MB of memory, since this is
  556. * the maximum mapped by the Linux kernel during initialization.
  557. */
  558. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  559. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  560. #ifdef CONFIG_CMD_KGDB
  561. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  562. #endif
  563. /*
  564. * Environment Configuration
  565. */
  566. #define CONFIG_ROOTPATH "/opt/nfsroot"
  567. #define CONFIG_BOOTFILE "uImage"
  568. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  569. /* default location for tftp and bootm */
  570. #define CONFIG_LOADADDR 1000000
  571. #define __USB_PHY_TYPE utmi
  572. #define CONFIG_EXTRA_ENV_SETTINGS \
  573. "hwconfig=fsl_ddr:bank_intlv=auto;" \
  574. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  575. "netdev=eth0\0" \
  576. "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
  577. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  578. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  579. "tftpflash=tftpboot $loadaddr $uboot && " \
  580. "protect off $ubootaddr +$filesize && " \
  581. "erase $ubootaddr +$filesize && " \
  582. "cp.b $loadaddr $ubootaddr $filesize && " \
  583. "protect on $ubootaddr +$filesize && " \
  584. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  585. "consoledev=ttyS0\0" \
  586. "ramdiskaddr=2000000\0" \
  587. "ramdiskfile=t1040qds/ramdisk.uboot\0" \
  588. "fdtaddr=1e00000\0" \
  589. "fdtfile=t1040qds/t1040qds.dtb\0" \
  590. "bdev=sda3\0"
  591. #define CONFIG_LINUX \
  592. "setenv bootargs root=/dev/ram rw " \
  593. "console=$consoledev,$baudrate $othbootargs;" \
  594. "setenv ramdiskaddr 0x02000000;" \
  595. "setenv fdtaddr 0x00c00000;" \
  596. "setenv loadaddr 0x1000000;" \
  597. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  598. #define CONFIG_HDBOOT \
  599. "setenv bootargs root=/dev/$bdev rw " \
  600. "console=$consoledev,$baudrate $othbootargs;" \
  601. "tftp $loadaddr $bootfile;" \
  602. "tftp $fdtaddr $fdtfile;" \
  603. "bootm $loadaddr - $fdtaddr"
  604. #define CONFIG_NFSBOOTCOMMAND \
  605. "setenv bootargs root=/dev/nfs rw " \
  606. "nfsroot=$serverip:$rootpath " \
  607. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  608. "console=$consoledev,$baudrate $othbootargs;" \
  609. "tftp $loadaddr $bootfile;" \
  610. "tftp $fdtaddr $fdtfile;" \
  611. "bootm $loadaddr - $fdtaddr"
  612. #define CONFIG_RAMBOOTCOMMAND \
  613. "setenv bootargs root=/dev/ram rw " \
  614. "console=$consoledev,$baudrate $othbootargs;" \
  615. "tftp $ramdiskaddr $ramdiskfile;" \
  616. "tftp $loadaddr $bootfile;" \
  617. "tftp $fdtaddr $fdtfile;" \
  618. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  619. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  620. #include <asm/fsl_secure_boot.h>
  621. #endif /* __CONFIG_H */