T102xQDS.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T1024/T1023 QDS board configuration file
  7. */
  8. #ifndef __T1024QDS_H
  9. #define __T1024QDS_H
  10. /* High Level Configuration Options */
  11. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  12. #define CONFIG_MP /* support multiple processors */
  13. #define CONFIG_ENABLE_36BIT_PHYS
  14. #ifdef CONFIG_PHYS_64BIT
  15. #define CONFIG_ADDR_MAP 1
  16. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  17. #endif
  18. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  19. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  20. #define CONFIG_ENV_OVERWRITE
  21. #define CONFIG_DEEP_SLEEP
  22. #ifdef CONFIG_RAMBOOT_PBL
  23. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  24. #define CONFIG_SPL_FLUSH_IMAGE
  25. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  26. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  27. #define CONFIG_SPL_PAD_TO 0x40000
  28. #define CONFIG_SPL_MAX_SIZE 0x28000
  29. #define RESET_VECTOR_OFFSET 0x27FFC
  30. #define BOOT_PAGE_OFFSET 0x27000
  31. #ifdef CONFIG_SPL_BUILD
  32. #define CONFIG_SPL_SKIP_RELOCATE
  33. #define CONFIG_SPL_COMMON_INIT_DDR
  34. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  35. #endif
  36. #ifdef CONFIG_NAND
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  38. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  39. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  40. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  41. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  42. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  43. #define CONFIG_SPL_NAND_BOOT
  44. #endif
  45. #ifdef CONFIG_SPIFLASH
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  47. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  49. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  51. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  52. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  53. #ifndef CONFIG_SPL_BUILD
  54. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55. #endif
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  57. #define CONFIG_SPL_SPI_BOOT
  58. #endif
  59. #ifdef CONFIG_SDCARD
  60. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  61. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  62. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  63. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  64. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  65. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66. #ifndef CONFIG_SPL_BUILD
  67. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68. #endif
  69. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  70. #define CONFIG_SPL_MMC_BOOT
  71. #endif
  72. #endif /* CONFIG_RAMBOOT_PBL */
  73. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  75. #endif
  76. #ifdef CONFIG_MTD_NOR_FLASH
  77. #define CONFIG_FLASH_CFI_DRIVER
  78. #define CONFIG_SYS_FLASH_CFI
  79. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  80. #endif
  81. /* PCIe Boot - Master */
  82. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  83. /*
  84. * for slave u-boot IMAGE instored in master memory space,
  85. * PHYS must be aligned based on the SIZE
  86. */
  87. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  88. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  89. #ifdef CONFIG_PHYS_64BIT
  90. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  91. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  92. #else
  93. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  94. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  95. #endif
  96. /*
  97. * for slave UCODE and ENV instored in master memory space,
  98. * PHYS must be aligned based on the SIZE
  99. */
  100. #ifdef CONFIG_PHYS_64BIT
  101. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  102. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  103. #else
  104. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  105. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
  106. #endif
  107. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  108. /* slave core release by master*/
  109. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  110. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  111. /* PCIe Boot - Slave */
  112. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  113. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  114. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  115. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  116. /* Set 1M boot space for PCIe boot */
  117. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  118. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  119. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  120. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  121. #endif
  122. #if defined(CONFIG_SPIFLASH)
  123. #define CONFIG_SYS_EXTRA_ENV_RELOC
  124. #define CONFIG_ENV_SPI_BUS 0
  125. #define CONFIG_ENV_SPI_CS 0
  126. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  127. #define CONFIG_ENV_SPI_MODE 0
  128. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  129. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  130. #define CONFIG_ENV_SECT_SIZE 0x10000
  131. #elif defined(CONFIG_SDCARD)
  132. #define CONFIG_SYS_EXTRA_ENV_RELOC
  133. #define CONFIG_SYS_MMC_ENV_DEV 0
  134. #define CONFIG_ENV_SIZE 0x2000
  135. #define CONFIG_ENV_OFFSET (512 * 0x800)
  136. #elif defined(CONFIG_NAND)
  137. #define CONFIG_SYS_EXTRA_ENV_RELOC
  138. #define CONFIG_ENV_SIZE 0x2000
  139. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  140. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  141. #define CONFIG_ENV_ADDR 0xffe20000
  142. #define CONFIG_ENV_SIZE 0x2000
  143. #elif defined(CONFIG_ENV_IS_NOWHERE)
  144. #define CONFIG_ENV_SIZE 0x2000
  145. #else
  146. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  147. #define CONFIG_ENV_SIZE 0x2000
  148. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  149. #endif
  150. #ifndef __ASSEMBLY__
  151. unsigned long get_board_sys_clk(void);
  152. unsigned long get_board_ddr_clk(void);
  153. #endif
  154. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  155. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  156. /*
  157. * These can be toggled for performance analysis, otherwise use default.
  158. */
  159. #define CONFIG_SYS_CACHE_STASHING
  160. #define CONFIG_BACKSIDE_L2_CACHE
  161. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  162. #define CONFIG_BTB /* toggle branch predition */
  163. #define CONFIG_DDR_ECC
  164. #ifdef CONFIG_DDR_ECC
  165. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  166. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  167. #endif
  168. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  169. #define CONFIG_SYS_MEMTEST_END 0x00400000
  170. /*
  171. * Config the L3 Cache as L3 SRAM
  172. */
  173. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  174. #define CONFIG_SYS_L3_SIZE (256 << 10)
  175. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  176. #ifdef CONFIG_RAMBOOT_PBL
  177. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  178. #endif
  179. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  180. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  181. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  182. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  183. #ifdef CONFIG_PHYS_64BIT
  184. #define CONFIG_SYS_DCSRBAR 0xf0000000
  185. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  186. #endif
  187. /* EEPROM */
  188. #define CONFIG_ID_EEPROM
  189. #define CONFIG_SYS_I2C_EEPROM_NXID
  190. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  192. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  193. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  194. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  195. /*
  196. * DDR Setup
  197. */
  198. #define CONFIG_VERY_BIG_RAM
  199. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  200. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  201. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  202. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  203. #define CONFIG_DDR_SPD
  204. #define CONFIG_SYS_SPD_BUS_NUM 0
  205. #define SPD_EEPROM_ADDRESS 0x51
  206. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  207. /*
  208. * IFC Definitions
  209. */
  210. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  211. #ifdef CONFIG_PHYS_64BIT
  212. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  213. #else
  214. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  215. #endif
  216. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  217. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  218. + 0x8000000) | \
  219. CSPR_PORT_SIZE_16 | \
  220. CSPR_MSEL_NOR | \
  221. CSPR_V)
  222. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  223. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  224. CSPR_PORT_SIZE_16 | \
  225. CSPR_MSEL_NOR | \
  226. CSPR_V)
  227. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  228. /* NOR Flash Timing Params */
  229. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  230. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  231. FTIM0_NOR_TEADC(0x5) | \
  232. FTIM0_NOR_TEAHC(0x5))
  233. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  234. FTIM1_NOR_TRAD_NOR(0x1A) |\
  235. FTIM1_NOR_TSEQRAD_NOR(0x13))
  236. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  237. FTIM2_NOR_TCH(0x4) | \
  238. FTIM2_NOR_TWPH(0x0E) | \
  239. FTIM2_NOR_TWP(0x1c))
  240. #define CONFIG_SYS_NOR_FTIM3 0x0
  241. #define CONFIG_SYS_FLASH_QUIET_TEST
  242. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  243. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  244. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  245. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  246. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  247. #define CONFIG_SYS_FLASH_EMPTY_INFO
  248. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  249. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  250. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  251. #define QIXIS_BASE 0xffdf0000
  252. #ifdef CONFIG_PHYS_64BIT
  253. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  254. #else
  255. #define QIXIS_BASE_PHYS QIXIS_BASE
  256. #endif
  257. #define QIXIS_LBMAP_SWITCH 0x06
  258. #define QIXIS_LBMAP_MASK 0x0f
  259. #define QIXIS_LBMAP_SHIFT 0
  260. #define QIXIS_LBMAP_DFLTBANK 0x00
  261. #define QIXIS_LBMAP_ALTBANK 0x04
  262. #define QIXIS_RST_CTL_RESET 0x31
  263. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  264. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  265. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  266. #define QIXIS_RST_FORCE_MEM 0x01
  267. #define CONFIG_SYS_CSPR3_EXT (0xf)
  268. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  269. | CSPR_PORT_SIZE_8 \
  270. | CSPR_MSEL_GPCM \
  271. | CSPR_V)
  272. #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
  273. #define CONFIG_SYS_CSOR3 0x0
  274. /* QIXIS Timing parameters for IFC CS3 */
  275. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  276. FTIM0_GPCM_TEADC(0x0e) | \
  277. FTIM0_GPCM_TEAHC(0x0e))
  278. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  279. FTIM1_GPCM_TRAD(0x3f))
  280. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  281. FTIM2_GPCM_TCH(0x8) | \
  282. FTIM2_GPCM_TWP(0x1f))
  283. #define CONFIG_SYS_CS3_FTIM3 0x0
  284. #define CONFIG_NAND_FSL_IFC
  285. #define CONFIG_SYS_NAND_BASE 0xff800000
  286. #ifdef CONFIG_PHYS_64BIT
  287. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  288. #else
  289. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  290. #endif
  291. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  292. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  293. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  294. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  295. | CSPR_V)
  296. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  297. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  298. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  299. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  300. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  301. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  302. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  303. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  304. #define CONFIG_SYS_NAND_ONFI_DETECTION
  305. /* ONFI NAND Flash mode0 Timing Params */
  306. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  307. FTIM0_NAND_TWP(0x18) | \
  308. FTIM0_NAND_TWCHT(0x07) | \
  309. FTIM0_NAND_TWH(0x0a))
  310. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  311. FTIM1_NAND_TWBE(0x39) | \
  312. FTIM1_NAND_TRR(0x0e) | \
  313. FTIM1_NAND_TRP(0x18))
  314. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  315. FTIM2_NAND_TREH(0x0a) | \
  316. FTIM2_NAND_TWHRE(0x1e))
  317. #define CONFIG_SYS_NAND_FTIM3 0x0
  318. #define CONFIG_SYS_NAND_DDR_LAW 11
  319. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  320. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  321. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  322. #if defined(CONFIG_NAND)
  323. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  324. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  325. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  326. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  327. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  328. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  329. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  330. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  331. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  332. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  333. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  334. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  335. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  336. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  337. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  338. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  339. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  340. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  341. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  342. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  343. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  344. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  345. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  346. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  347. #else
  348. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  349. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  350. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  351. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  352. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  353. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  354. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  355. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  356. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  357. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  358. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  359. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  360. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  361. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  362. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  363. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  364. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  365. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  366. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  367. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  368. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  369. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  370. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  371. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  372. #endif
  373. #ifdef CONFIG_SPL_BUILD
  374. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  375. #else
  376. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  377. #endif
  378. #if defined(CONFIG_RAMBOOT_PBL)
  379. #define CONFIG_SYS_RAMBOOT
  380. #endif
  381. #define CONFIG_MISC_INIT_R
  382. #define CONFIG_HWCONFIG
  383. /* define to use L1 as initial stack */
  384. #define CONFIG_L1_INIT_RAM
  385. #define CONFIG_SYS_INIT_RAM_LOCK
  386. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  387. #ifdef CONFIG_PHYS_64BIT
  388. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  389. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  390. /* The assembler doesn't like typecast */
  391. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  392. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  393. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  394. #else
  395. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  396. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  397. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  398. #endif
  399. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  400. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  401. GENERATED_GBL_DATA_SIZE)
  402. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  403. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  404. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  405. /* Serial Port */
  406. #define CONFIG_SYS_NS16550_SERIAL
  407. #define CONFIG_SYS_NS16550_REG_SIZE 1
  408. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  409. #define CONFIG_SYS_BAUDRATE_TABLE \
  410. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  411. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  412. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  413. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  414. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  415. /* Video */
  416. #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
  417. #define CONFIG_FSL_DIU_FB
  418. #ifdef CONFIG_FSL_DIU_FB
  419. #define CONFIG_FSL_DIU_CH7301
  420. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  421. #define CONFIG_VIDEO_LOGO
  422. #define CONFIG_VIDEO_BMP_LOGO
  423. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  424. /*
  425. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  426. * disable empty flash sector detection, which is I/O-intensive.
  427. */
  428. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  429. #endif
  430. #endif
  431. /* I2C */
  432. #define CONFIG_SYS_I2C
  433. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  434. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  435. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  436. #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
  437. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  438. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  439. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  440. #define I2C_MUX_PCA_ADDR 0x77
  441. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  442. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  443. #define I2C_RETIMER_ADDR 0x18
  444. /* I2C bus multiplexer */
  445. #define I2C_MUX_CH_DEFAULT 0x8
  446. #define I2C_MUX_CH_DIU 0xC
  447. #define I2C_MUX_CH5 0xD
  448. #define I2C_MUX_CH7 0xF
  449. /* LDI/DVI Encoder for display */
  450. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  451. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  452. /*
  453. * RTC configuration
  454. */
  455. #define RTC
  456. #define CONFIG_RTC_DS3231 1
  457. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  458. /*
  459. * eSPI - Enhanced SPI
  460. */
  461. #ifndef CONFIG_SPL_BUILD
  462. #endif
  463. #define CONFIG_SPI_FLASH_BAR
  464. #define CONFIG_SF_DEFAULT_SPEED 10000000
  465. #define CONFIG_SF_DEFAULT_MODE 0
  466. /*
  467. * General PCIe
  468. * Memory space is mapped 1-1, but I/O space must start from 0.
  469. */
  470. #define CONFIG_PCIE1 /* PCIE controller 1 */
  471. #define CONFIG_PCIE2 /* PCIE controller 2 */
  472. #define CONFIG_PCIE3 /* PCIE controller 3 */
  473. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  474. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  475. #define CONFIG_PCI_INDIRECT_BRIDGE
  476. #ifdef CONFIG_PCI
  477. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  478. #ifdef CONFIG_PCIE1
  479. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  480. #ifdef CONFIG_PHYS_64BIT
  481. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  482. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  483. #else
  484. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  485. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  486. #endif
  487. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  488. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  489. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  490. #ifdef CONFIG_PHYS_64BIT
  491. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  492. #else
  493. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  494. #endif
  495. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  496. #endif
  497. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  498. #ifdef CONFIG_PCIE2
  499. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  500. #ifdef CONFIG_PHYS_64BIT
  501. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  502. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  503. #else
  504. #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
  505. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
  506. #endif
  507. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  508. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  509. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  510. #ifdef CONFIG_PHYS_64BIT
  511. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  512. #else
  513. #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  514. #endif
  515. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  516. #endif
  517. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  518. #ifdef CONFIG_PCIE3
  519. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  520. #ifdef CONFIG_PHYS_64BIT
  521. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  522. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  523. #else
  524. #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  525. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
  526. #endif
  527. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  528. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  529. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  530. #ifdef CONFIG_PHYS_64BIT
  531. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  532. #else
  533. #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  534. #endif
  535. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  536. #endif
  537. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  538. #endif /* CONFIG_PCI */
  539. /*
  540. *SATA
  541. */
  542. #define CONFIG_FSL_SATA_V2
  543. #ifdef CONFIG_FSL_SATA_V2
  544. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  545. #define CONFIG_SATA1
  546. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  547. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  548. #define CONFIG_LBA48
  549. #endif
  550. /*
  551. * USB
  552. */
  553. #define CONFIG_HAS_FSL_DR_USB
  554. #ifdef CONFIG_HAS_FSL_DR_USB
  555. #define CONFIG_USB_EHCI_FSL
  556. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  557. #endif
  558. /*
  559. * SDHC
  560. */
  561. #ifdef CONFIG_MMC
  562. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  563. #endif
  564. /* Qman/Bman */
  565. #ifndef CONFIG_NOBQFMAN
  566. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  567. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  568. #ifdef CONFIG_PHYS_64BIT
  569. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  570. #else
  571. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  572. #endif
  573. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  574. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  575. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  576. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  577. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  578. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  579. CONFIG_SYS_BMAN_CENA_SIZE)
  580. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  581. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  582. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  583. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  584. #ifdef CONFIG_PHYS_64BIT
  585. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  586. #else
  587. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  588. #endif
  589. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  590. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  591. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  592. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  593. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  594. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  595. CONFIG_SYS_QMAN_CENA_SIZE)
  596. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  597. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  598. #define CONFIG_SYS_DPAA_FMAN
  599. #define CONFIG_QE
  600. #define CONFIG_U_QE
  601. /* Default address of microcode for the Linux FMan driver */
  602. #if defined(CONFIG_SPIFLASH)
  603. /*
  604. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  605. * env, so we got 0x110000.
  606. */
  607. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  608. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  609. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  610. #elif defined(CONFIG_SDCARD)
  611. /*
  612. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  613. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  614. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  615. */
  616. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  617. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  618. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  619. #elif defined(CONFIG_NAND)
  620. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  621. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  622. #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  623. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  624. /*
  625. * Slave has no ucode locally, it can fetch this from remote. When implementing
  626. * in two corenet boards, slave's ucode could be stored in master's memory
  627. * space, the address can be mapped from slave TLB->slave LAW->
  628. * slave SRIO or PCIE outbound window->master inbound window->
  629. * master LAW->the ucode address in master's memory space.
  630. */
  631. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  632. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  633. #else
  634. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  635. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  636. #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
  637. #endif
  638. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  639. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  640. #endif /* CONFIG_NOBQFMAN */
  641. #ifdef CONFIG_SYS_DPAA_FMAN
  642. #define CONFIG_FMAN_ENET
  643. #define CONFIG_PHYLIB_10G
  644. #define CONFIG_PHY_VITESSE
  645. #define CONFIG_PHY_REALTEK
  646. #define CONFIG_PHY_TERANETICS
  647. #define RGMII_PHY1_ADDR 0x1
  648. #define RGMII_PHY2_ADDR 0x2
  649. #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
  650. #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
  651. #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
  652. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  653. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  654. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  655. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  656. #endif
  657. #ifdef CONFIG_FMAN_ENET
  658. #define CONFIG_MII /* MII PHY management */
  659. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  660. #endif
  661. /*
  662. * Dynamic MTD Partition support with mtdparts
  663. */
  664. #ifdef CONFIG_MTD_NOR_FLASH
  665. #define CONFIG_MTD_DEVICE
  666. #define CONFIG_MTD_PARTITIONS
  667. #define CONFIG_FLASH_CFI_MTD
  668. #endif
  669. /*
  670. * Environment
  671. */
  672. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  673. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  674. /*
  675. * Miscellaneous configurable options
  676. */
  677. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  678. /*
  679. * For booting Linux, the board info and command line data
  680. * have to be in the first 64 MB of memory, since this is
  681. * the maximum mapped by the Linux kernel during initialization.
  682. */
  683. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  684. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  685. #ifdef CONFIG_CMD_KGDB
  686. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  687. #endif
  688. /*
  689. * Environment Configuration
  690. */
  691. #define CONFIG_ROOTPATH "/opt/nfsroot"
  692. #define CONFIG_BOOTFILE "uImage"
  693. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  694. #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
  695. #define __USB_PHY_TYPE utmi
  696. #define CONFIG_EXTRA_ENV_SETTINGS \
  697. "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
  698. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  699. "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
  700. "ramdiskfile=t1024qds/ramdisk.uboot\0" \
  701. "fdtfile=t1024qds/t1024qds.dtb\0" \
  702. "netdev=eth0\0" \
  703. "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
  704. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  705. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  706. "tftpflash=tftpboot $loadaddr $uboot && " \
  707. "protect off $ubootaddr +$filesize && " \
  708. "erase $ubootaddr +$filesize && " \
  709. "cp.b $loadaddr $ubootaddr $filesize && " \
  710. "protect on $ubootaddr +$filesize && " \
  711. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  712. "consoledev=ttyS0\0" \
  713. "ramdiskaddr=2000000\0" \
  714. "fdtaddr=d00000\0" \
  715. "bdev=sda3\0"
  716. #define CONFIG_LINUX \
  717. "setenv bootargs root=/dev/ram rw " \
  718. "console=$consoledev,$baudrate $othbootargs;" \
  719. "setenv ramdiskaddr 0x02000000;" \
  720. "setenv fdtaddr 0x00c00000;" \
  721. "setenv loadaddr 0x1000000;" \
  722. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  723. #define CONFIG_NFSBOOTCOMMAND \
  724. "setenv bootargs root=/dev/nfs rw " \
  725. "nfsroot=$serverip:$rootpath " \
  726. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  727. "console=$consoledev,$baudrate $othbootargs;" \
  728. "tftp $loadaddr $bootfile;" \
  729. "tftp $fdtaddr $fdtfile;" \
  730. "bootm $loadaddr - $fdtaddr"
  731. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  732. #include <asm/fsl_secure_boot.h>
  733. #endif /* __T1024QDS_H */