P2041RDB.h 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * P2041 RDB board configuration file
  7. * Also supports P2040 RDB
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #ifdef CONFIG_RAMBOOT_PBL
  12. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  13. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  14. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  15. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  16. #endif
  17. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  18. /* Set 1M boot space */
  19. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  20. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  21. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  22. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  23. #endif
  24. /* High Level Configuration Options */
  25. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  26. #define CONFIG_MP /* support multiple processors */
  27. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  28. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  29. #endif
  30. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  31. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  32. #define CONFIG_PCIE1 /* PCIE controller 1 */
  33. #define CONFIG_PCIE2 /* PCIE controller 2 */
  34. #define CONFIG_PCIE3 /* PCIE controller 3 */
  35. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  36. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  37. #define CONFIG_SYS_SRIO
  38. #define CONFIG_SRIO1 /* SRIO port 1 */
  39. #define CONFIG_SRIO2 /* SRIO port 2 */
  40. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  41. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  42. #define CONFIG_ENV_OVERWRITE
  43. #ifndef CONFIG_MTD_NOR_FLASH
  44. #else
  45. #define CONFIG_FLASH_CFI_DRIVER
  46. #define CONFIG_SYS_FLASH_CFI
  47. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  48. #endif
  49. #if defined(CONFIG_SPIFLASH)
  50. #define CONFIG_SYS_EXTRA_ENV_RELOC
  51. #define CONFIG_ENV_SPI_BUS 0
  52. #define CONFIG_ENV_SPI_CS 0
  53. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  54. #define CONFIG_ENV_SPI_MODE 0
  55. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  56. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  57. #define CONFIG_ENV_SECT_SIZE 0x10000
  58. #elif defined(CONFIG_SDCARD)
  59. #define CONFIG_SYS_EXTRA_ENV_RELOC
  60. #define CONFIG_FSL_FIXED_MMC_LOCATION
  61. #define CONFIG_SYS_MMC_ENV_DEV 0
  62. #define CONFIG_ENV_SIZE 0x2000
  63. #define CONFIG_ENV_OFFSET (512 * 1658)
  64. #elif defined(CONFIG_NAND)
  65. #define CONFIG_SYS_EXTRA_ENV_RELOC
  66. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  67. #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  68. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  69. #define CONFIG_ENV_ADDR 0xffe20000
  70. #define CONFIG_ENV_SIZE 0x2000
  71. #elif defined(CONFIG_ENV_IS_NOWHERE)
  72. #define CONFIG_ENV_SIZE 0x2000
  73. #else
  74. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
  75. - CONFIG_ENV_SECT_SIZE)
  76. #define CONFIG_ENV_SIZE 0x2000
  77. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  78. #endif
  79. #ifndef __ASSEMBLY__
  80. unsigned long get_board_sys_clk(unsigned long dummy);
  81. #endif
  82. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  83. /*
  84. * These can be toggled for performance analysis, otherwise use default.
  85. */
  86. #define CONFIG_SYS_CACHE_STASHING
  87. #define CONFIG_BACKSIDE_L2_CACHE
  88. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  89. #define CONFIG_BTB /* toggle branch predition */
  90. #define CONFIG_ENABLE_36BIT_PHYS
  91. #ifdef CONFIG_PHYS_64BIT
  92. #define CONFIG_ADDR_MAP
  93. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  94. #endif
  95. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  96. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  97. #define CONFIG_SYS_MEMTEST_END 0x00400000
  98. /*
  99. * Config the L3 Cache as L3 SRAM
  100. */
  101. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  102. #ifdef CONFIG_PHYS_64BIT
  103. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  104. CONFIG_RAMBOOT_TEXT_BASE)
  105. #else
  106. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  107. #endif
  108. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  109. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  110. #ifdef CONFIG_PHYS_64BIT
  111. #define CONFIG_SYS_DCSRBAR 0xf0000000
  112. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  113. #endif
  114. /* EEPROM */
  115. #define CONFIG_ID_EEPROM
  116. #define CONFIG_SYS_I2C_EEPROM_NXID
  117. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  118. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  119. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  120. /*
  121. * DDR Setup
  122. */
  123. #define CONFIG_VERY_BIG_RAM
  124. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  125. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  126. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  127. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  128. #define CONFIG_DDR_SPD
  129. #define CONFIG_SYS_SPD_BUS_NUM 0
  130. #define SPD_EEPROM_ADDRESS 0x52
  131. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  132. /*
  133. * Local Bus Definitions
  134. */
  135. /* Set the local bus clock 1/8 of platform clock */
  136. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  137. /*
  138. * This board doesn't have a promjet connector.
  139. * However, it uses commone corenet board LAW and TLB.
  140. * It is necessary to use the same start address with proper offset.
  141. */
  142. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  143. #ifdef CONFIG_PHYS_64BIT
  144. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  145. #else
  146. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  147. #endif
  148. #define CONFIG_SYS_FLASH_BR_PRELIM \
  149. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
  150. BR_PS_16 | BR_V)
  151. #define CONFIG_SYS_FLASH_OR_PRELIM \
  152. ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  153. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  154. #define CONFIG_FSL_CPLD
  155. #define CPLD_BASE 0xffdf0000 /* CPLD registers */
  156. #ifdef CONFIG_PHYS_64BIT
  157. #define CPLD_BASE_PHYS 0xfffdf0000ull
  158. #else
  159. #define CPLD_BASE_PHYS CPLD_BASE
  160. #endif
  161. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
  162. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  163. #define PIXIS_LBMAP_SWITCH 7
  164. #define PIXIS_LBMAP_MASK 0xf0
  165. #define PIXIS_LBMAP_SHIFT 4
  166. #define PIXIS_LBMAP_ALTBANK 0x40
  167. #define CONFIG_SYS_FLASH_QUIET_TEST
  168. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  169. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  170. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  171. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
  172. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
  173. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  174. #if defined(CONFIG_RAMBOOT_PBL)
  175. #define CONFIG_SYS_RAMBOOT
  176. #endif
  177. #define CONFIG_NAND_FSL_ELBC
  178. /* Nand Flash */
  179. #ifdef CONFIG_NAND_FSL_ELBC
  180. #define CONFIG_SYS_NAND_BASE 0xffa00000
  181. #ifdef CONFIG_PHYS_64BIT
  182. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  183. #else
  184. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  185. #endif
  186. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  187. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  188. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  189. /* NAND flash config */
  190. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  191. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  192. | BR_PS_8 /* Port Size = 8 bit */ \
  193. | BR_MS_FCM /* MSEL = FCM */ \
  194. | BR_V) /* valid */
  195. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  196. | OR_FCM_PGS /* Large Page*/ \
  197. | OR_FCM_CSCT \
  198. | OR_FCM_CST \
  199. | OR_FCM_CHT \
  200. | OR_FCM_SCY_1 \
  201. | OR_FCM_TRLX \
  202. | OR_FCM_EHTR)
  203. #ifdef CONFIG_NAND
  204. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  205. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  206. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  207. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  208. #else
  209. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  210. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  211. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  212. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  213. #endif
  214. #else
  215. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  216. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  217. #endif /* CONFIG_NAND_FSL_ELBC */
  218. #define CONFIG_SYS_FLASH_EMPTY_INFO
  219. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  220. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  221. #define CONFIG_MISC_INIT_R
  222. #define CONFIG_HWCONFIG
  223. /* define to use L1 as initial stack */
  224. #define CONFIG_L1_INIT_RAM
  225. #define CONFIG_SYS_INIT_RAM_LOCK
  226. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  227. #ifdef CONFIG_PHYS_64BIT
  228. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  229. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  230. /* The assembler doesn't like typecast */
  231. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  232. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  233. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  234. #else
  235. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  236. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  237. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  238. #endif
  239. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  240. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  241. GENERATED_GBL_DATA_SIZE)
  242. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  243. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  244. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  245. /* Serial Port - controlled on board with jumper J8
  246. * open - index 2
  247. * shorted - index 1
  248. */
  249. #define CONFIG_SYS_NS16550_SERIAL
  250. #define CONFIG_SYS_NS16550_REG_SIZE 1
  251. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  252. #define CONFIG_SYS_BAUDRATE_TABLE \
  253. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  254. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  255. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  256. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  257. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  258. /* I2C */
  259. #define CONFIG_SYS_I2C
  260. #define CONFIG_SYS_I2C_FSL
  261. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  262. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  263. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  264. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  265. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  266. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  267. /*
  268. * RapidIO
  269. */
  270. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  271. #ifdef CONFIG_PHYS_64BIT
  272. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  273. #else
  274. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  275. #endif
  276. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  277. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  278. #ifdef CONFIG_PHYS_64BIT
  279. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  280. #else
  281. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  282. #endif
  283. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  284. /*
  285. * for slave u-boot IMAGE instored in master memory space,
  286. * PHYS must be aligned based on the SIZE
  287. */
  288. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  289. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  290. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  291. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  292. /*
  293. * for slave UCODE and ENV instored in master memory space,
  294. * PHYS must be aligned based on the SIZE
  295. */
  296. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  297. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  298. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  299. /* slave core release by master*/
  300. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  301. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  302. /*
  303. * SRIO_PCIE_BOOT - SLAVE
  304. */
  305. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  306. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  307. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  308. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  309. #endif
  310. /*
  311. * eSPI - Enhanced SPI
  312. */
  313. #define CONFIG_SF_DEFAULT_SPEED 10000000
  314. #define CONFIG_SF_DEFAULT_MODE 0
  315. /*
  316. * General PCI
  317. * Memory space is mapped 1-1, but I/O space must start from 0.
  318. */
  319. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  320. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  321. #ifdef CONFIG_PHYS_64BIT
  322. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  323. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  324. #else
  325. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  326. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  327. #endif
  328. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  329. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  330. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  331. #ifdef CONFIG_PHYS_64BIT
  332. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  333. #else
  334. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  335. #endif
  336. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  337. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  338. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  339. #ifdef CONFIG_PHYS_64BIT
  340. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  341. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  342. #else
  343. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  344. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  345. #endif
  346. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  347. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  348. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  349. #ifdef CONFIG_PHYS_64BIT
  350. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  351. #else
  352. #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  353. #endif
  354. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  355. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  356. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  357. #ifdef CONFIG_PHYS_64BIT
  358. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  359. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  360. #else
  361. #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
  362. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
  363. #endif
  364. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  365. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  366. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  367. #ifdef CONFIG_PHYS_64BIT
  368. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  369. #else
  370. #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  371. #endif
  372. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  373. /* Qman/Bman */
  374. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  375. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  376. #ifdef CONFIG_PHYS_64BIT
  377. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  378. #else
  379. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  380. #endif
  381. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  382. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  383. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  384. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  385. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  386. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  387. CONFIG_SYS_BMAN_CENA_SIZE)
  388. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  389. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  390. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  391. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  392. #ifdef CONFIG_PHYS_64BIT
  393. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  394. #else
  395. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  396. #endif
  397. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  398. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  399. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  400. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  401. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  402. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  403. CONFIG_SYS_QMAN_CENA_SIZE)
  404. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  405. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  406. #define CONFIG_SYS_DPAA_FMAN
  407. #define CONFIG_SYS_DPAA_PME
  408. /* Default address of microcode for the Linux Fman driver */
  409. #if defined(CONFIG_SPIFLASH)
  410. /*
  411. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  412. * env, so we got 0x110000.
  413. */
  414. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  415. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  416. #elif defined(CONFIG_SDCARD)
  417. /*
  418. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  419. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  420. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  421. */
  422. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  423. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  424. #elif defined(CONFIG_NAND)
  425. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  426. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  427. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  428. /*
  429. * Slave has no ucode locally, it can fetch this from remote. When implementing
  430. * in two corenet boards, slave's ucode could be stored in master's memory
  431. * space, the address can be mapped from slave TLB->slave LAW->
  432. * slave SRIO or PCIE outbound window->master inbound window->
  433. * master LAW->the ucode address in master's memory space.
  434. */
  435. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  436. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  437. #else
  438. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  439. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  440. #endif
  441. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  442. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  443. #ifdef CONFIG_SYS_DPAA_FMAN
  444. #define CONFIG_FMAN_ENET
  445. #define CONFIG_PHYLIB_10G
  446. #define CONFIG_PHY_VITESSE
  447. #define CONFIG_PHY_TERANETICS
  448. #endif
  449. #ifdef CONFIG_PCI
  450. #define CONFIG_PCI_INDIRECT_BRIDGE
  451. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  452. #endif /* CONFIG_PCI */
  453. /* SATA */
  454. #define CONFIG_FSL_SATA_V2
  455. #ifdef CONFIG_FSL_SATA_V2
  456. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  457. #define CONFIG_SATA1
  458. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  459. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  460. #define CONFIG_SATA2
  461. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  462. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  463. #define CONFIG_LBA48
  464. #endif
  465. #ifdef CONFIG_FMAN_ENET
  466. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
  467. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
  468. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
  469. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
  470. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
  471. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  472. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  473. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  474. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  475. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
  476. #define CONFIG_SYS_TBIPA_VALUE 8
  477. #define CONFIG_MII /* MII PHY management */
  478. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  479. #endif
  480. /*
  481. * Environment
  482. */
  483. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  484. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  485. /*
  486. * Command line configuration.
  487. */
  488. /*
  489. * USB
  490. */
  491. #define CONFIG_HAS_FSL_DR_USB
  492. #define CONFIG_HAS_FSL_MPH_USB
  493. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  494. #define CONFIG_USB_EHCI_FSL
  495. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  496. #endif
  497. #ifdef CONFIG_MMC
  498. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  499. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  500. #endif
  501. /*
  502. * Miscellaneous configurable options
  503. */
  504. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  505. /*
  506. * For booting Linux, the board info and command line data
  507. * have to be in the first 64 MB of memory, since this is
  508. * the maximum mapped by the Linux kernel during initialization.
  509. */
  510. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  511. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  512. #ifdef CONFIG_CMD_KGDB
  513. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  514. #endif
  515. /*
  516. * Environment Configuration
  517. */
  518. #define CONFIG_ROOTPATH "/opt/nfsroot"
  519. #define CONFIG_BOOTFILE "uImage"
  520. #define CONFIG_UBOOTPATH u-boot.bin
  521. /* default location for tftp and bootm */
  522. #define CONFIG_LOADADDR 1000000
  523. #define __USB_PHY_TYPE utmi
  524. #define CONFIG_EXTRA_ENV_SETTINGS \
  525. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  526. "bank_intlv=cs0_cs1\0" \
  527. "netdev=eth0\0" \
  528. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  529. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  530. "tftpflash=tftpboot $loadaddr $uboot && " \
  531. "protect off $ubootaddr +$filesize && " \
  532. "erase $ubootaddr +$filesize && " \
  533. "cp.b $loadaddr $ubootaddr $filesize && " \
  534. "protect on $ubootaddr +$filesize && " \
  535. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  536. "consoledev=ttyS0\0" \
  537. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  538. "usb_dr_mode=host\0" \
  539. "ramdiskaddr=2000000\0" \
  540. "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
  541. "fdtaddr=1e00000\0" \
  542. "fdtfile=p2041rdb/p2041rdb.dtb\0" \
  543. "bdev=sda3\0"
  544. #define CONFIG_HDBOOT \
  545. "setenv bootargs root=/dev/$bdev rw " \
  546. "console=$consoledev,$baudrate $othbootargs;" \
  547. "tftp $loadaddr $bootfile;" \
  548. "tftp $fdtaddr $fdtfile;" \
  549. "bootm $loadaddr - $fdtaddr"
  550. #define CONFIG_NFSBOOTCOMMAND \
  551. "setenv bootargs root=/dev/nfs rw " \
  552. "nfsroot=$serverip:$rootpath " \
  553. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  554. "console=$consoledev,$baudrate $othbootargs;" \
  555. "tftp $loadaddr $bootfile;" \
  556. "tftp $fdtaddr $fdtfile;" \
  557. "bootm $loadaddr - $fdtaddr"
  558. #define CONFIG_RAMBOOTCOMMAND \
  559. "setenv bootargs root=/dev/ram rw " \
  560. "console=$consoledev,$baudrate $othbootargs;" \
  561. "tftp $ramdiskaddr $ramdiskfile;" \
  562. "tftp $loadaddr $bootfile;" \
  563. "tftp $fdtaddr $fdtfile;" \
  564. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  565. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  566. #include <asm/fsl_secure_boot.h>
  567. #endif /* __CONFIG_H */