MPC8641HPCN.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2006, 2010-2011 Freescale Semiconductor.
  4. *
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. /*
  8. * MPC8641HPCN board configuration file
  9. *
  10. * Make sure you change the MAC address and other network params first,
  11. * search for CONFIG_SERVERIP, etc. in this file.
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. /* High Level Configuration Options */
  16. #define CONFIG_MP 1 /* support multiple processors */
  17. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  18. #define CONFIG_ADDR_MAP 1 /* Use addr map */
  19. /*
  20. * default CCSRBAR is at 0xff700000
  21. * assume U-Boot is less than 0.5MB
  22. */
  23. #ifdef RUN_DIAG
  24. #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
  25. #endif
  26. /*
  27. * virtual address to be used for temporary mappings. There
  28. * should be 128k free at this VA.
  29. */
  30. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  31. #define CONFIG_SYS_SRIO
  32. #define CONFIG_SRIO1 /* SRIO port 1 */
  33. #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
  34. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
  35. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  36. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  37. #define CONFIG_ENV_OVERWRITE
  38. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  39. #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
  40. #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
  41. #define CONFIG_ALTIVEC 1
  42. /*
  43. * L2CR setup -- make sure this is right for your board!
  44. */
  45. #define CONFIG_SYS_L2
  46. #define L2_INIT 0
  47. #define L2_ENABLE (L2CR_L2E)
  48. #ifndef CONFIG_SYS_CLK_FREQ
  49. #ifndef __ASSEMBLY__
  50. extern unsigned long get_board_sys_clk(unsigned long dummy);
  51. #endif
  52. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  53. #endif
  54. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  55. #define CONFIG_SYS_MEMTEST_END 0x00400000
  56. /*
  57. * With the exception of PCI Memory and Rapid IO, most devices will simply
  58. * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  59. * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
  60. */
  61. #ifdef CONFIG_PHYS_64BIT
  62. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  63. #else
  64. #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  65. #endif
  66. /*
  67. * Base addresses -- Note these are effective addresses where the
  68. * actual resources get mapped (not physical addresses)
  69. */
  70. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  71. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  72. /* Physical addresses */
  73. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  74. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
  75. #define CONFIG_SYS_CCSRBAR_PHYS \
  76. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  77. CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  78. #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  79. /*
  80. * DDR Setup
  81. */
  82. #define CONFIG_FSL_DDR_INTERACTIVE
  83. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  84. #define CONFIG_DDR_SPD
  85. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  86. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  87. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  88. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  89. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  90. #define CONFIG_VERY_BIG_RAM
  91. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  92. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  93. /*
  94. * I2C addresses of SPD EEPROMs
  95. */
  96. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  97. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
  98. #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
  99. #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
  100. /*
  101. * These are used when DDR doesn't use SPD.
  102. */
  103. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  104. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  105. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  106. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  107. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  108. #define CONFIG_SYS_DDR_TIMING_1 0x39357322
  109. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  110. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  111. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  112. #define CONFIG_SYS_DDR_INTERVAL 0x06090100
  113. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  114. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  115. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  116. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  117. #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
  118. #define CONFIG_SYS_DDR_CONTROL2 0x04400000
  119. #define CONFIG_ID_EEPROM
  120. #define CONFIG_SYS_I2C_EEPROM_NXID
  121. #define CONFIG_ID_EEPROM
  122. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  123. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  124. #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
  125. #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
  126. #define CONFIG_SYS_FLASH_BASE_PHYS \
  127. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  128. CONFIG_SYS_PHYS_ADDR_HIGH)
  129. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  130. #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  131. | 0x00001001) /* port size 16bit */
  132. #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
  133. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
  134. | 0x00001001) /* port size 16bit */
  135. #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
  136. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
  137. | 0x00000801) /* port size 8bit */
  138. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
  139. /*
  140. * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
  141. * The PIXIS and CF by themselves aren't large enough to take up the 128k
  142. * required for the smallest BAT mapping, so there's a 64k hole.
  143. */
  144. #define CONFIG_SYS_LBC_BASE 0xffde0000
  145. #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
  146. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  147. #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
  148. #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
  149. #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
  150. CONFIG_SYS_PHYS_ADDR_HIGH)
  151. #define PIXIS_SIZE 0x00008000 /* 32k */
  152. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  153. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  154. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  155. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  156. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
  157. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  158. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  159. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  160. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  161. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  162. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  163. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  164. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  165. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  166. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  167. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  168. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  169. /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
  170. #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
  171. #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
  172. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  173. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  174. #undef CONFIG_SYS_FLASH_CHECKSUM
  175. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  176. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  177. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  178. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  179. #define CONFIG_FLASH_CFI_DRIVER
  180. #define CONFIG_SYS_FLASH_CFI
  181. #define CONFIG_SYS_FLASH_EMPTY_INFO
  182. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  183. #define CONFIG_SYS_RAMBOOT
  184. #else
  185. #undef CONFIG_SYS_RAMBOOT
  186. #endif
  187. #if defined(CONFIG_SYS_RAMBOOT)
  188. #undef CONFIG_SPD_EEPROM
  189. #define CONFIG_SYS_SDRAM_SIZE 256
  190. #endif
  191. #undef CONFIG_CLOCKS_IN_MHZ
  192. #define CONFIG_SYS_INIT_RAM_LOCK 1
  193. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  194. #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
  195. #else
  196. #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
  197. #endif
  198. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  199. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  200. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  201. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  202. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  203. /* Serial Port */
  204. #define CONFIG_SYS_NS16550_SERIAL
  205. #define CONFIG_SYS_NS16550_REG_SIZE 1
  206. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  207. #define CONFIG_SYS_BAUDRATE_TABLE \
  208. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  209. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  210. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  211. /*
  212. * I2C
  213. */
  214. #define CONFIG_SYS_I2C
  215. #define CONFIG_SYS_I2C_FSL
  216. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  217. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  218. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  219. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  220. /*
  221. * RapidIO MMU
  222. */
  223. #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
  224. #ifdef CONFIG_PHYS_64BIT
  225. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
  226. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
  227. #else
  228. #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
  229. #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
  230. #endif
  231. #define CONFIG_SYS_SRIO1_MEM_PHYS \
  232. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  233. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
  234. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
  235. /*
  236. * General PCI
  237. * Addresses are mapped 1-1.
  238. */
  239. #define CONFIG_SYS_PCIE1_NAME "ULI"
  240. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  241. #ifdef CONFIG_PHYS_64BIT
  242. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  243. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
  244. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
  245. #else
  246. #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
  247. #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
  248. #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
  249. #endif
  250. #define CONFIG_SYS_PCIE1_MEM_PHYS \
  251. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  252. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
  253. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  254. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  255. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  256. #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
  257. #define CONFIG_SYS_PCIE1_IO_PHYS \
  258. PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  259. CONFIG_SYS_PHYS_ADDR_HIGH)
  260. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
  261. #ifdef CONFIG_PHYS_64BIT
  262. /*
  263. * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
  264. * This will increase the amount of PCI address space available for
  265. * for mapping RAM.
  266. */
  267. #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
  268. #else
  269. #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
  270. + CONFIG_SYS_PCIE1_MEM_SIZE)
  271. #endif
  272. #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
  273. + CONFIG_SYS_PCIE1_MEM_SIZE)
  274. #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
  275. + CONFIG_SYS_PCIE1_MEM_SIZE)
  276. #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
  277. #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
  278. + CONFIG_SYS_PCIE1_MEM_SIZE)
  279. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  280. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  281. #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
  282. + CONFIG_SYS_PCIE1_IO_SIZE)
  283. #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
  284. + CONFIG_SYS_PCIE1_IO_SIZE)
  285. #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
  286. + CONFIG_SYS_PCIE1_IO_SIZE)
  287. #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
  288. #if defined(CONFIG_PCI)
  289. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  290. #undef CONFIG_EEPRO100
  291. #undef CONFIG_TULIP
  292. /************************************************************
  293. * USB support
  294. ************************************************************/
  295. #define CONFIG_PCI_OHCI 1
  296. #define CONFIG_USB_OHCI_NEW 1
  297. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  298. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  299. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  300. /*PCIE video card used*/
  301. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  302. /*PCI video card used*/
  303. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
  304. /* video */
  305. #if defined(CONFIG_VIDEO)
  306. #define CONFIG_BIOSEMU
  307. #define CONFIG_ATI_RADEON_FB
  308. #define CONFIG_VIDEO_LOGO
  309. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
  310. #endif
  311. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  312. #ifdef CONFIG_SCSI_AHCI
  313. #define CONFIG_SATA_ULI5288
  314. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  315. #define CONFIG_SYS_SCSI_MAX_LUN 1
  316. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  317. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  318. #endif
  319. #endif /* CONFIG_PCI */
  320. #if defined(CONFIG_TSEC_ENET)
  321. #define CONFIG_MII 1 /* MII PHY management */
  322. #define CONFIG_TSEC1 1
  323. #define CONFIG_TSEC1_NAME "eTSEC1"
  324. #define CONFIG_TSEC2 1
  325. #define CONFIG_TSEC2_NAME "eTSEC2"
  326. #define CONFIG_TSEC3 1
  327. #define CONFIG_TSEC3_NAME "eTSEC3"
  328. #define CONFIG_TSEC4 1
  329. #define CONFIG_TSEC4_NAME "eTSEC4"
  330. #define TSEC1_PHY_ADDR 0
  331. #define TSEC2_PHY_ADDR 1
  332. #define TSEC3_PHY_ADDR 2
  333. #define TSEC4_PHY_ADDR 3
  334. #define TSEC1_PHYIDX 0
  335. #define TSEC2_PHYIDX 0
  336. #define TSEC3_PHYIDX 0
  337. #define TSEC4_PHYIDX 0
  338. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  339. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  340. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  341. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  342. #define CONFIG_ETHPRIME "eTSEC1"
  343. #endif /* CONFIG_TSEC_ENET */
  344. #ifdef CONFIG_PHYS_64BIT
  345. #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
  346. #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
  347. /* Put physical address into the BAT format */
  348. #define BAT_PHYS_ADDR(low, high) \
  349. (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
  350. /* Convert high/low pairs to actual 64-bit value */
  351. #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
  352. #else
  353. /* 32-bit systems just ignore the "high" bits */
  354. #define BAT_PHYS_ADDR(low, high) (low)
  355. #define PAIRED_PHYS_TO_PHYS(low, high) (low)
  356. #endif
  357. /*
  358. * BAT0 DDR
  359. */
  360. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  361. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  362. /*
  363. * BAT1 LBC (PIXIS/CF)
  364. */
  365. #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  366. CONFIG_SYS_PHYS_ADDR_HIGH) \
  367. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  368. BATL_GUARDEDSTORAGE)
  369. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
  370. | BATU_VS | BATU_VP)
  371. #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
  372. CONFIG_SYS_PHYS_ADDR_HIGH) \
  373. | BATL_PP_RW | BATL_MEMCOHERENCE)
  374. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  375. /* if CONFIG_PCI:
  376. * BAT2 PCIE1 and PCIE1 MEM
  377. * if CONFIG_RIO
  378. * BAT2 Rapidio Memory
  379. */
  380. #ifdef CONFIG_PCI
  381. #define CONFIG_PCI_INDIRECT_BRIDGE
  382. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  383. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  384. | BATL_PP_RW | BATL_CACHEINHIBIT \
  385. | BATL_GUARDEDSTORAGE)
  386. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
  387. | BATU_VS | BATU_VP)
  388. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
  389. CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
  390. | BATL_PP_RW | BATL_CACHEINHIBIT)
  391. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  392. #else /* CONFIG_RIO */
  393. #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  394. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  395. | BATL_PP_RW | BATL_CACHEINHIBIT | \
  396. BATL_GUARDEDSTORAGE)
  397. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
  398. | BATU_VS | BATU_VP)
  399. #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
  400. CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
  401. | BATL_PP_RW | BATL_CACHEINHIBIT)
  402. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  403. #endif
  404. /*
  405. * BAT3 CCSR Space
  406. */
  407. #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  408. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  409. | BATL_PP_RW | BATL_CACHEINHIBIT \
  410. | BATL_GUARDEDSTORAGE)
  411. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
  412. | BATU_VP)
  413. #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  414. CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
  415. | BATL_PP_RW | BATL_CACHEINHIBIT)
  416. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  417. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  418. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  419. | BATL_PP_RW | BATL_CACHEINHIBIT \
  420. | BATL_GUARDEDSTORAGE)
  421. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  422. | BATU_BL_1M | BATU_VS | BATU_VP)
  423. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  424. | BATL_PP_RW | BATL_CACHEINHIBIT)
  425. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  426. #endif
  427. /*
  428. * BAT4 PCIE1_IO and PCIE2_IO
  429. */
  430. #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  431. CONFIG_SYS_PHYS_ADDR_HIGH) \
  432. | BATL_PP_RW | BATL_CACHEINHIBIT \
  433. | BATL_GUARDEDSTORAGE)
  434. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
  435. | BATU_VS | BATU_VP)
  436. #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
  437. CONFIG_SYS_PHYS_ADDR_HIGH) \
  438. | BATL_PP_RW | BATL_CACHEINHIBIT)
  439. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  440. /*
  441. * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
  442. */
  443. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  444. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  445. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  446. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  447. /*
  448. * BAT6 FLASH
  449. */
  450. #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  451. CONFIG_SYS_PHYS_ADDR_HIGH) \
  452. | BATL_PP_RW | BATL_CACHEINHIBIT \
  453. | BATL_GUARDEDSTORAGE)
  454. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
  455. | BATU_VP)
  456. #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
  457. CONFIG_SYS_PHYS_ADDR_HIGH) \
  458. | BATL_PP_RW | BATL_MEMCOHERENCE)
  459. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  460. /* Map the last 1M of flash where we're running from reset */
  461. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  462. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  463. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  464. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  465. | BATL_MEMCOHERENCE)
  466. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  467. /*
  468. * BAT7 FREE - used later for tmp mappings
  469. */
  470. #define CONFIG_SYS_DBAT7L 0x00000000
  471. #define CONFIG_SYS_DBAT7U 0x00000000
  472. #define CONFIG_SYS_IBAT7L 0x00000000
  473. #define CONFIG_SYS_IBAT7U 0x00000000
  474. /*
  475. * Environment
  476. */
  477. #ifndef CONFIG_SYS_RAMBOOT
  478. #define CONFIG_ENV_ADDR \
  479. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  480. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  481. #else
  482. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  483. #endif
  484. #define CONFIG_ENV_SIZE 0x2000
  485. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  486. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  487. /*
  488. * BOOTP options
  489. */
  490. #define CONFIG_BOOTP_BOOTFILESIZE
  491. #undef CONFIG_WATCHDOG /* watchdog disabled */
  492. /*
  493. * Miscellaneous configurable options
  494. */
  495. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  496. /*
  497. * For booting Linux, the board info and command line data
  498. * have to be in the first 8 MB of memory, since this is
  499. * the maximum mapped by the Linux kernel during initialization.
  500. */
  501. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
  502. #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
  503. #if defined(CONFIG_CMD_KGDB)
  504. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  505. #endif
  506. /*
  507. * Environment Configuration
  508. */
  509. #define CONFIG_HAS_ETH0 1
  510. #define CONFIG_HAS_ETH1 1
  511. #define CONFIG_HAS_ETH2 1
  512. #define CONFIG_HAS_ETH3 1
  513. #define CONFIG_IPADDR 192.168.1.100
  514. #define CONFIG_HOSTNAME "unknown"
  515. #define CONFIG_ROOTPATH "/opt/nfsroot"
  516. #define CONFIG_BOOTFILE "uImage"
  517. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  518. #define CONFIG_SERVERIP 192.168.1.1
  519. #define CONFIG_GATEWAYIP 192.168.1.1
  520. #define CONFIG_NETMASK 255.255.255.0
  521. /* default location for tftp and bootm */
  522. #define CONFIG_LOADADDR 0x10000000
  523. #define CONFIG_EXTRA_ENV_SETTINGS \
  524. "netdev=eth0\0" \
  525. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  526. "tftpflash=tftpboot $loadaddr $uboot; " \
  527. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  528. " +$filesize; " \
  529. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  530. " +$filesize; " \
  531. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  532. " $filesize; " \
  533. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  534. " +$filesize; " \
  535. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  536. " $filesize\0" \
  537. "consoledev=ttyS0\0" \
  538. "ramdiskaddr=0x18000000\0" \
  539. "ramdiskfile=your.ramdisk.u-boot\0" \
  540. "fdtaddr=0x17c00000\0" \
  541. "fdtfile=mpc8641_hpcn.dtb\0" \
  542. "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
  543. "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
  544. "maxcpus=2"
  545. #define CONFIG_NFSBOOTCOMMAND \
  546. "setenv bootargs root=/dev/nfs rw " \
  547. "nfsroot=$serverip:$rootpath " \
  548. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  549. "console=$consoledev,$baudrate $othbootargs;" \
  550. "tftp $loadaddr $bootfile;" \
  551. "tftp $fdtaddr $fdtfile;" \
  552. "bootm $loadaddr - $fdtaddr"
  553. #define CONFIG_RAMBOOTCOMMAND \
  554. "setenv bootargs root=/dev/ram rw " \
  555. "console=$consoledev,$baudrate $othbootargs;" \
  556. "tftp $ramdiskaddr $ramdiskfile;" \
  557. "tftp $loadaddr $bootfile;" \
  558. "tftp $fdtaddr $fdtfile;" \
  559. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  560. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  561. #endif /* __CONFIG_H */