MPC8569MDS.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8569mds board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_SYS_SRIO
  11. #define CONFIG_SRIO1 /* SRIO port 1 */
  12. #define CONFIG_PCIE1 1 /* PCIE controller */
  13. #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
  14. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  15. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  16. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  17. #define CONFIG_QE /* Enable QE */
  18. #define CONFIG_ENV_OVERWRITE
  19. #ifndef __ASSEMBLY__
  20. extern unsigned long get_clock_freq(void);
  21. #endif
  22. /* Replace a call to get_clock_freq (after it is implemented)*/
  23. #define CONFIG_SYS_CLK_FREQ 66666666
  24. #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
  25. #ifdef CONFIG_ATM
  26. #define CONFIG_PQ_MDS_PIB
  27. #define CONFIG_PQ_MDS_PIB_ATM
  28. #endif
  29. /*
  30. * These can be toggled for performance analysis, otherwise use default.
  31. */
  32. #define CONFIG_L2_CACHE /* toggle L2 cache */
  33. #define CONFIG_BTB /* toggle branch predition */
  34. #ifndef CONFIG_SYS_MONITOR_BASE
  35. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  36. #endif
  37. /*
  38. * Only possible on E500 Version 2 or newer cores.
  39. */
  40. #define CONFIG_ENABLE_36BIT_PHYS 1
  41. #define CONFIG_HWCONFIG
  42. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  43. #define CONFIG_SYS_MEMTEST_END 0x00400000
  44. /*
  45. * Config the L2 Cache as L2 SRAM
  46. */
  47. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  48. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  49. #define CONFIG_SYS_L2_SIZE (512 << 10)
  50. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  51. #define CONFIG_SYS_CCSRBAR 0xe0000000
  52. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  53. #if defined(CONFIG_NAND_SPL)
  54. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  55. #endif
  56. /* DDR Setup */
  57. #undef CONFIG_FSL_DDR_INTERACTIVE
  58. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  59. #define CONFIG_DDR_SPD
  60. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  61. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  62. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  63. /* DDR is system memory*/
  64. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  65. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  66. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  67. /* I2C addresses of SPD EEPROMs */
  68. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  69. /* These are used when DDR doesn't use SPD. */
  70. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
  71. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  72. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  73. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  74. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  75. #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
  76. #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
  77. #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
  78. #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
  79. #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
  80. #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
  81. #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
  82. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  83. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
  84. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  85. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  86. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  87. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
  88. #define CONFIG_SYS_DDR_CDR_1 0x80040000
  89. #define CONFIG_SYS_DDR_CDR_2 0x00000000
  90. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  91. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  92. #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
  93. #define CONFIG_SYS_DDR_CONTROL2 0x24400000
  94. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  95. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  96. #define CONFIG_SYS_DDR_SBE 0x00010000
  97. #undef CONFIG_CLOCKS_IN_MHZ
  98. /*
  99. * Local Bus Definitions
  100. */
  101. #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
  102. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  103. #define CONFIG_SYS_BCSR_BASE 0xf8000000
  104. #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
  105. /*Chip select 0 - Flash*/
  106. #define CONFIG_FLASH_BR_PRELIM 0xfe000801
  107. #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
  108. /*Chip select 1 - BCSR*/
  109. #define CONFIG_SYS_BR1_PRELIM 0xf8000801
  110. #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
  111. /*Chip select 4 - PIB*/
  112. #define CONFIG_SYS_BR4_PRELIM 0xf8008801
  113. #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
  114. /*Chip select 5 - PIB*/
  115. #define CONFIG_SYS_BR5_PRELIM 0xf8010801
  116. #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
  117. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  118. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  119. #undef CONFIG_SYS_FLASH_CHECKSUM
  120. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  121. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  122. #undef CONFIG_SYS_RAMBOOT
  123. #define CONFIG_FLASH_CFI_DRIVER
  124. #define CONFIG_SYS_FLASH_CFI
  125. #define CONFIG_SYS_FLASH_EMPTY_INFO
  126. /* Chip select 3 - NAND */
  127. #ifndef CONFIG_NAND_SPL
  128. #define CONFIG_SYS_NAND_BASE 0xFC000000
  129. #else
  130. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  131. #endif
  132. /* NAND boot: 4K NAND loader config */
  133. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  134. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
  135. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  136. #define CONFIG_SYS_NAND_U_BOOT_START \
  137. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  138. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  139. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  140. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  141. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  142. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
  143. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  144. #define CONFIG_NAND_FSL_ELBC 1
  145. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  146. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  147. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  148. | BR_PS_8 /* Port Size = 8 bit */ \
  149. | BR_MS_FCM /* MSEL = FCM */ \
  150. | BR_V) /* valid */
  151. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  152. | OR_FCM_CSCT \
  153. | OR_FCM_CST \
  154. | OR_FCM_CHT \
  155. | OR_FCM_SCY_1 \
  156. | OR_FCM_TRLX \
  157. | OR_FCM_EHTR)
  158. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  159. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  160. #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  161. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  162. #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
  163. #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
  164. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  165. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  166. #define CONFIG_SYS_INIT_RAM_LOCK 1
  167. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  168. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  169. #define CONFIG_SYS_GBL_DATA_OFFSET \
  170. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  171. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  172. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  173. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  174. /* Serial Port */
  175. #define CONFIG_SYS_NS16550_SERIAL
  176. #define CONFIG_SYS_NS16550_REG_SIZE 1
  177. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  178. #ifdef CONFIG_NAND_SPL
  179. #define CONFIG_NS16550_MIN_FUNCTIONS
  180. #endif
  181. #define CONFIG_SYS_BAUDRATE_TABLE \
  182. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  183. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  184. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  185. /*
  186. * I2C
  187. */
  188. #define CONFIG_SYS_I2C
  189. #define CONFIG_SYS_I2C_FSL
  190. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  191. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  192. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  193. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  194. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  195. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  196. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  197. /*
  198. * I2C2 EEPROM
  199. */
  200. #define CONFIG_ID_EEPROM
  201. #ifdef CONFIG_ID_EEPROM
  202. #define CONFIG_SYS_I2C_EEPROM_NXID
  203. #endif
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  205. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  206. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  207. #define PLPPAR1_I2C_BIT_MASK 0x0000000F
  208. #define PLPPAR1_I2C2_VAL 0x00000000
  209. #define PLPPAR1_ESDHC_VAL 0x0000000A
  210. #define PLPDIR1_I2C_BIT_MASK 0x0000000F
  211. #define PLPDIR1_I2C2_VAL 0x0000000F
  212. #define PLPDIR1_ESDHC_VAL 0x00000006
  213. #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
  214. #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
  215. #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
  216. #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
  217. /*
  218. * General PCI
  219. * Memory Addresses are mapped 1-1. I/O is mapped from 0
  220. */
  221. #define CONFIG_SYS_PCIE1_NAME "Slot"
  222. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  223. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  224. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  225. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  226. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  227. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  228. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  229. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  230. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
  231. #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
  232. #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
  233. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
  234. #ifdef CONFIG_QE
  235. /*
  236. * QE UEC ethernet configuration
  237. */
  238. #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
  239. #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
  240. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  241. #define CONFIG_UEC_ETH
  242. #define CONFIG_ETHPRIME "UEC0"
  243. #define CONFIG_PHY_MODE_NEED_CHANGE
  244. #define CONFIG_UEC_ETH1 /* GETH1 */
  245. #define CONFIG_HAS_ETH0
  246. #ifdef CONFIG_UEC_ETH1
  247. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  248. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
  249. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  250. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
  251. #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
  252. #define CONFIG_SYS_UEC1_PHY_ADDR 7
  253. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  254. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
  255. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  256. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
  257. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  258. #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
  259. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  260. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  261. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  262. #endif /* CONFIG_UEC_ETH1 */
  263. #define CONFIG_UEC_ETH2 /* GETH2 */
  264. #define CONFIG_HAS_ETH1
  265. #ifdef CONFIG_UEC_ETH2
  266. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  267. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
  268. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  269. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
  270. #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
  271. #define CONFIG_SYS_UEC2_PHY_ADDR 1
  272. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  273. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
  274. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  275. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
  276. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  277. #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
  278. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  279. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  280. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  281. #endif /* CONFIG_UEC_ETH2 */
  282. #define CONFIG_UEC_ETH3 /* GETH3 */
  283. #define CONFIG_HAS_ETH2
  284. #ifdef CONFIG_UEC_ETH3
  285. #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
  286. #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
  287. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  288. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
  289. #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
  290. #define CONFIG_SYS_UEC3_PHY_ADDR 2
  291. #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  292. #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
  293. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  294. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
  295. #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
  296. #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
  297. #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  298. #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
  299. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  300. #endif /* CONFIG_UEC_ETH3 */
  301. #define CONFIG_UEC_ETH4 /* GETH4 */
  302. #define CONFIG_HAS_ETH3
  303. #ifdef CONFIG_UEC_ETH4
  304. #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
  305. #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
  306. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  307. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
  308. #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
  309. #define CONFIG_SYS_UEC4_PHY_ADDR 3
  310. #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  311. #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
  312. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  313. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
  314. #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
  315. #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
  316. #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  317. #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
  318. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  319. #endif /* CONFIG_UEC_ETH4 */
  320. #undef CONFIG_UEC_ETH6 /* GETH6 */
  321. #define CONFIG_HAS_ETH5
  322. #ifdef CONFIG_UEC_ETH6
  323. #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
  324. #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
  325. #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
  326. #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
  327. #define CONFIG_SYS_UEC6_PHY_ADDR 4
  328. #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
  329. #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
  330. #endif /* CONFIG_UEC_ETH6 */
  331. #undef CONFIG_UEC_ETH8 /* GETH8 */
  332. #define CONFIG_HAS_ETH7
  333. #ifdef CONFIG_UEC_ETH8
  334. #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
  335. #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
  336. #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
  337. #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
  338. #define CONFIG_SYS_UEC8_PHY_ADDR 6
  339. #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
  340. #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
  341. #endif /* CONFIG_UEC_ETH8 */
  342. #endif /* CONFIG_QE */
  343. #if defined(CONFIG_PCI)
  344. #undef CONFIG_EEPRO100
  345. #undef CONFIG_TULIP
  346. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  347. #endif /* CONFIG_PCI */
  348. /*
  349. * Environment
  350. */
  351. #if defined(CONFIG_SYS_RAMBOOT)
  352. #else
  353. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  354. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  355. #define CONFIG_ENV_SIZE 0x2000
  356. #endif
  357. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  358. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  359. /* QE microcode/firmware address */
  360. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  361. #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
  362. /*
  363. * BOOTP options
  364. */
  365. #define CONFIG_BOOTP_BOOTFILESIZE
  366. #undef CONFIG_WATCHDOG /* watchdog disabled */
  367. #ifdef CONFIG_MMC
  368. #define CONFIG_FSL_ESDHC_PIN_MUX
  369. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  370. #endif
  371. /*
  372. * Miscellaneous configurable options
  373. */
  374. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  375. #if defined(CONFIG_CMD_KGDB)
  376. #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
  377. #else
  378. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  379. #endif
  380. #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  381. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  382. /* Boot Argument Buffer Size */
  383. /*
  384. * For booting Linux, the board info and command line data
  385. * have to be in the first 64 MB of memory, since this is
  386. * the maximum mapped by the Linux kernel during initialization.
  387. */
  388. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  389. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  390. #if defined(CONFIG_CMD_KGDB)
  391. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  392. #endif
  393. /*
  394. * Environment Configuration
  395. */
  396. #define CONFIG_HOSTNAME "mpc8569mds"
  397. #define CONFIG_ROOTPATH "/nfsroot"
  398. #define CONFIG_BOOTFILE "your.uImage"
  399. #define CONFIG_SERVERIP 192.168.1.1
  400. #define CONFIG_GATEWAYIP 192.168.1.1
  401. #define CONFIG_NETMASK 255.255.255.0
  402. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  403. #define CONFIG_EXTRA_ENV_SETTINGS \
  404. "netdev=eth0\0" \
  405. "consoledev=ttyS0\0" \
  406. "ramdiskaddr=600000\0" \
  407. "ramdiskfile=your.ramdisk.u-boot\0" \
  408. "fdtaddr=400000\0" \
  409. "fdtfile=your.fdt.dtb\0" \
  410. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  411. "nfsroot=$serverip:$rootpath " \
  412. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  413. "console=$consoledev,$baudrate $othbootargs\0" \
  414. "ramargs=setenv bootargs root=/dev/ram rw " \
  415. "console=$consoledev,$baudrate $othbootargs\0" \
  416. #define CONFIG_NFSBOOTCOMMAND \
  417. "run nfsargs;" \
  418. "tftp $loadaddr $bootfile;" \
  419. "tftp $fdtaddr $fdtfile;" \
  420. "bootm $loadaddr - $fdtaddr"
  421. #define CONFIG_RAMBOOTCOMMAND \
  422. "run ramargs;" \
  423. "tftp $ramdiskaddr $ramdiskfile;" \
  424. "tftp $loadaddr $bootfile;" \
  425. "bootm $loadaddr $ramdiskaddr"
  426. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  427. #endif /* __CONFIG_H */