MPC8349EMDS.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2010
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * mpc8349emds board configuration file
  8. *
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_E300 1 /* E300 Family */
  16. #define CONFIG_MPC834x 1 /* MPC834x family */
  17. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  18. #define CONFIG_PCI_66M
  19. #ifdef CONFIG_PCI_66M
  20. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  21. #else
  22. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  23. #endif
  24. #ifdef CONFIG_PCISLAVE
  25. #define CONFIG_83XX_PCICLK 66666666 /* in Hz */
  26. #endif /* CONFIG_PCISLAVE */
  27. #ifndef CONFIG_SYS_CLK_FREQ
  28. #ifdef CONFIG_PCI_66M
  29. #define CONFIG_SYS_CLK_FREQ 66000000
  30. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  31. #else
  32. #define CONFIG_SYS_CLK_FREQ 33000000
  33. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  34. #endif
  35. #endif
  36. #define CONFIG_SYS_IMMR 0xE0000000
  37. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  38. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  39. #define CONFIG_SYS_MEMTEST_END 0x00100000
  40. /*
  41. * DDR Setup
  42. */
  43. #define CONFIG_DDR_ECC /* support DDR ECC function */
  44. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  45. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  46. /*
  47. * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  48. * unselect it to use old spd_sdram.c
  49. */
  50. #define CONFIG_SYS_SPD_BUS_NUM 0
  51. #define SPD_EEPROM_ADDRESS1 0x52
  52. #define SPD_EEPROM_ADDRESS2 0x51
  53. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  54. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  55. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  56. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  57. /*
  58. * 32-bit data path mode.
  59. *
  60. * Please note that using this mode for devices with the real density of 64-bit
  61. * effectively reduces the amount of available memory due to the effect of
  62. * wrapping around while translating address to row/columns, for example in the
  63. * 256MB module the upper 128MB get aliased with contents of the lower
  64. * 128MB); normally this define should be used for devices with real 32-bit
  65. * data path.
  66. */
  67. #undef CONFIG_DDR_32BIT
  68. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  69. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  70. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  71. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  72. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  73. #undef CONFIG_DDR_2T_TIMING
  74. /*
  75. * DDRCDR - DDR Control Driver Register
  76. */
  77. #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  78. #if defined(CONFIG_SPD_EEPROM)
  79. /*
  80. * Determine DDR configuration from I2C interface.
  81. */
  82. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  83. #else
  84. /*
  85. * Manually set up DDR parameters
  86. */
  87. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  88. #if defined(CONFIG_DDR_II)
  89. #define CONFIG_SYS_DDRCDR 0x80080001
  90. #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
  91. #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
  92. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  93. #define CONFIG_SYS_DDR_TIMING_1 0x38357322
  94. #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
  95. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  96. #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
  97. #define CONFIG_SYS_DDR_MODE 0x47d00432
  98. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  99. #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
  100. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  101. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  102. #else
  103. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  104. | CSCONFIG_ROW_BIT_13 \
  105. | CSCONFIG_COL_BIT_10)
  106. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  107. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  108. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  109. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  110. #if defined(CONFIG_DDR_32BIT)
  111. /* set burst length to 8 for 32-bit data path */
  112. /* DLL,normal,seq,4/2.5, 8 burst len */
  113. #define CONFIG_SYS_DDR_MODE 0x00000023
  114. #else
  115. /* the default burst length is 4 - for 64-bit data path */
  116. /* DLL,normal,seq,4/2.5, 4 burst len */
  117. #define CONFIG_SYS_DDR_MODE 0x00000022
  118. #endif
  119. #endif
  120. #endif
  121. /*
  122. * SDRAM on the Local Bus
  123. */
  124. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  125. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  126. /*
  127. * FLASH on the Local Bus
  128. */
  129. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  130. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  131. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  132. #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
  133. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  134. /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
  135. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  136. | BR_PS_16 /* 16 bit port */ \
  137. | BR_MS_GPCM /* MSEL = GPCM */ \
  138. | BR_V) /* valid */
  139. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  140. | OR_UPM_XAM \
  141. | OR_GPCM_CSNT \
  142. | OR_GPCM_ACS_DIV2 \
  143. | OR_GPCM_XACS \
  144. | OR_GPCM_SCY_15 \
  145. | OR_GPCM_TRLX_SET \
  146. | OR_GPCM_EHTR_SET \
  147. | OR_GPCM_EAD)
  148. /* window base at flash base */
  149. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  150. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
  151. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  152. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  153. #undef CONFIG_SYS_FLASH_CHECKSUM
  154. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  155. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  156. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  157. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  158. #define CONFIG_SYS_RAMBOOT
  159. #else
  160. #undef CONFIG_SYS_RAMBOOT
  161. #endif
  162. /*
  163. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  164. */
  165. #define CONFIG_SYS_BCSR 0xE2400000
  166. /* Access window base at BCSR base */
  167. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
  168. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  169. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
  170. | BR_PS_8 \
  171. | BR_MS_GPCM \
  172. | BR_V)
  173. /* 0x00000801 */
  174. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
  175. | OR_GPCM_XAM \
  176. | OR_GPCM_CSNT \
  177. | OR_GPCM_SCY_15 \
  178. | OR_GPCM_TRLX_CLEAR \
  179. | OR_GPCM_EHTR_CLEAR)
  180. /* 0xFFFFE8F0 */
  181. #define CONFIG_SYS_INIT_RAM_LOCK 1
  182. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  183. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  184. #define CONFIG_SYS_GBL_DATA_OFFSET \
  185. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  186. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  187. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  188. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  189. /*
  190. * Local Bus LCRR and LBCR regs
  191. * LCRR: DLL bypass, Clock divider is 4
  192. * External Local Bus rate is
  193. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  194. */
  195. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  196. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  197. #define CONFIG_SYS_LBC_LBCR 0x00000000
  198. /*
  199. * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  200. * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
  201. */
  202. #undef CONFIG_SYS_LB_SDRAM
  203. #ifdef CONFIG_SYS_LB_SDRAM
  204. /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
  205. /*
  206. * Base Register 2 and Option Register 2 configure SDRAM.
  207. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  208. *
  209. * For BR2, need:
  210. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  211. * port-size = 32-bits = BR2[19:20] = 11
  212. * no parity checking = BR2[21:22] = 00
  213. * SDRAM for MSEL = BR2[24:26] = 011
  214. * Valid = BR[31] = 1
  215. *
  216. * 0 4 8 12 16 20 24 28
  217. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  218. */
  219. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  220. | BR_PS_32 /* 32-bit port */ \
  221. | BR_MS_SDRAM /* MSEL = SDRAM */ \
  222. | BR_V) /* Valid */
  223. /* 0xF0001861 */
  224. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  225. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  226. /*
  227. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  228. *
  229. * For OR2, need:
  230. * 64MB mask for AM, OR2[0:7] = 1111 1100
  231. * XAM, OR2[17:18] = 11
  232. * 9 columns OR2[19-21] = 010
  233. * 13 rows OR2[23-25] = 100
  234. * EAD set for extra time OR[31] = 1
  235. *
  236. * 0 4 8 12 16 20 24 28
  237. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  238. */
  239. #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
  240. | OR_SDRAM_XAM \
  241. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  242. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  243. | OR_SDRAM_EAD)
  244. /* 0xFC006901 */
  245. /* LB sdram refresh timer, about 6us */
  246. #define CONFIG_SYS_LBC_LSRT 0x32000000
  247. /* LB refresh timer prescal, 266MHz/32 */
  248. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  249. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  250. | LSDMR_BSMA1516 \
  251. | LSDMR_RFCR8 \
  252. | LSDMR_PRETOACT6 \
  253. | LSDMR_ACTTORW3 \
  254. | LSDMR_BL8 \
  255. | LSDMR_WRC3 \
  256. | LSDMR_CL3)
  257. /*
  258. * SDRAM Controller configuration sequence.
  259. */
  260. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  261. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  262. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  263. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  264. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  265. #endif
  266. /*
  267. * Serial Port
  268. */
  269. #define CONFIG_SYS_NS16550_SERIAL
  270. #define CONFIG_SYS_NS16550_REG_SIZE 1
  271. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  272. #define CONFIG_SYS_BAUDRATE_TABLE \
  273. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  274. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  275. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  276. /* I2C */
  277. #define CONFIG_SYS_I2C
  278. #define CONFIG_SYS_I2C_FSL
  279. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  280. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  281. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  282. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  283. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  284. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  285. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  286. /* SPI */
  287. #undef CONFIG_SOFT_SPI /* SPI bit-banged */
  288. /* GPIOs. Used as SPI chip selects */
  289. #define CONFIG_SYS_GPIO1_PRELIM
  290. #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
  291. #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
  292. /* TSEC */
  293. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  294. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  295. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  296. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  297. /* USB */
  298. #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
  299. /*
  300. * General PCI
  301. * Addresses are mapped 1-1.
  302. */
  303. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  304. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  305. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  306. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  307. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  308. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  309. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  310. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  311. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  312. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  313. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  314. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  315. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  316. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  317. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  318. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  319. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  320. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  321. #if defined(CONFIG_PCI)
  322. #define PCI_ONE_PCI1
  323. #if defined(PCI_64BIT)
  324. #undef PCI_ALL_PCI1
  325. #undef PCI_TWO_PCI1
  326. #undef PCI_ONE_PCI1
  327. #endif
  328. #define CONFIG_83XX_PCI_STREAMING
  329. #undef CONFIG_EEPRO100
  330. #undef CONFIG_TULIP
  331. #if !defined(CONFIG_PCI_PNP)
  332. #define PCI_ENET0_IOADDR 0xFIXME
  333. #define PCI_ENET0_MEMADDR 0xFIXME
  334. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  335. #endif
  336. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  337. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  338. #endif /* CONFIG_PCI */
  339. /*
  340. * TSEC configuration
  341. */
  342. #if defined(CONFIG_TSEC_ENET)
  343. #define CONFIG_GMII 1 /* MII PHY management */
  344. #define CONFIG_TSEC1 1
  345. #define CONFIG_TSEC1_NAME "TSEC0"
  346. #define CONFIG_TSEC2 1
  347. #define CONFIG_TSEC2_NAME "TSEC1"
  348. #define TSEC1_PHY_ADDR 0
  349. #define TSEC2_PHY_ADDR 1
  350. #define TSEC1_PHYIDX 0
  351. #define TSEC2_PHYIDX 0
  352. #define TSEC1_FLAGS TSEC_GIGABIT
  353. #define TSEC2_FLAGS TSEC_GIGABIT
  354. /* Options are: TSEC[0-1] */
  355. #define CONFIG_ETHPRIME "TSEC0"
  356. #endif /* CONFIG_TSEC_ENET */
  357. /*
  358. * Configure on-board RTC
  359. */
  360. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  361. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  362. /*
  363. * Environment
  364. */
  365. #ifndef CONFIG_SYS_RAMBOOT
  366. #define CONFIG_ENV_ADDR \
  367. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  368. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  369. #define CONFIG_ENV_SIZE 0x2000
  370. /* Address and size of Redundant Environment Sector */
  371. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  372. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  373. #else
  374. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  375. #define CONFIG_ENV_SIZE 0x2000
  376. #endif
  377. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  378. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  379. /*
  380. * BOOTP options
  381. */
  382. #define CONFIG_BOOTP_BOOTFILESIZE
  383. /*
  384. * Command line configuration.
  385. */
  386. #undef CONFIG_WATCHDOG /* watchdog disabled */
  387. /*
  388. * Miscellaneous configurable options
  389. */
  390. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  391. /*
  392. * For booting Linux, the board info and command line data
  393. * have to be in the first 256 MB of memory, since this is
  394. * the maximum mapped by the Linux kernel during initialization.
  395. */
  396. /* Initial Memory map for Linux*/
  397. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  398. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  399. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  400. #if 1 /*528/264*/
  401. #define CONFIG_SYS_HRCW_LOW (\
  402. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  403. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  404. HRCWL_CSB_TO_CLKIN |\
  405. HRCWL_VCO_1X2 |\
  406. HRCWL_CORE_TO_CSB_2X1)
  407. #elif 0 /*396/132*/
  408. #define CONFIG_SYS_HRCW_LOW (\
  409. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  410. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  411. HRCWL_CSB_TO_CLKIN |\
  412. HRCWL_VCO_1X4 |\
  413. HRCWL_CORE_TO_CSB_3X1)
  414. #elif 0 /*264/132*/
  415. #define CONFIG_SYS_HRCW_LOW (\
  416. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  417. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  418. HRCWL_CSB_TO_CLKIN |\
  419. HRCWL_VCO_1X4 |\
  420. HRCWL_CORE_TO_CSB_2X1)
  421. #elif 0 /*132/132*/
  422. #define CONFIG_SYS_HRCW_LOW (\
  423. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  424. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  425. HRCWL_CSB_TO_CLKIN |\
  426. HRCWL_VCO_1X4 |\
  427. HRCWL_CORE_TO_CSB_1X1)
  428. #elif 0 /*264/264 */
  429. #define CONFIG_SYS_HRCW_LOW (\
  430. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  431. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  432. HRCWL_CSB_TO_CLKIN |\
  433. HRCWL_VCO_1X4 |\
  434. HRCWL_CORE_TO_CSB_1X1)
  435. #endif
  436. #ifdef CONFIG_PCISLAVE
  437. #define CONFIG_SYS_HRCW_HIGH (\
  438. HRCWH_PCI_AGENT |\
  439. HRCWH_64_BIT_PCI |\
  440. HRCWH_PCI1_ARBITER_DISABLE |\
  441. HRCWH_PCI2_ARBITER_DISABLE |\
  442. HRCWH_CORE_ENABLE |\
  443. HRCWH_FROM_0X00000100 |\
  444. HRCWH_BOOTSEQ_DISABLE |\
  445. HRCWH_SW_WATCHDOG_DISABLE |\
  446. HRCWH_ROM_LOC_LOCAL_16BIT |\
  447. HRCWH_TSEC1M_IN_GMII |\
  448. HRCWH_TSEC2M_IN_GMII)
  449. #else
  450. #if defined(PCI_64BIT)
  451. #define CONFIG_SYS_HRCW_HIGH (\
  452. HRCWH_PCI_HOST |\
  453. HRCWH_64_BIT_PCI |\
  454. HRCWH_PCI1_ARBITER_ENABLE |\
  455. HRCWH_PCI2_ARBITER_DISABLE |\
  456. HRCWH_CORE_ENABLE |\
  457. HRCWH_FROM_0X00000100 |\
  458. HRCWH_BOOTSEQ_DISABLE |\
  459. HRCWH_SW_WATCHDOG_DISABLE |\
  460. HRCWH_ROM_LOC_LOCAL_16BIT |\
  461. HRCWH_TSEC1M_IN_GMII |\
  462. HRCWH_TSEC2M_IN_GMII)
  463. #else
  464. #define CONFIG_SYS_HRCW_HIGH (\
  465. HRCWH_PCI_HOST |\
  466. HRCWH_32_BIT_PCI |\
  467. HRCWH_PCI1_ARBITER_ENABLE |\
  468. HRCWH_PCI2_ARBITER_ENABLE |\
  469. HRCWH_CORE_ENABLE |\
  470. HRCWH_FROM_0X00000100 |\
  471. HRCWH_BOOTSEQ_DISABLE |\
  472. HRCWH_SW_WATCHDOG_DISABLE |\
  473. HRCWH_ROM_LOC_LOCAL_16BIT |\
  474. HRCWH_TSEC1M_IN_GMII |\
  475. HRCWH_TSEC2M_IN_GMII)
  476. #endif /* PCI_64BIT */
  477. #endif /* CONFIG_PCISLAVE */
  478. /*
  479. * System performance
  480. */
  481. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  482. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  483. #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
  484. #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
  485. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  486. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  487. /* System IO Config */
  488. #define CONFIG_SYS_SICRH 0
  489. #define CONFIG_SYS_SICRL SICRL_LDP_A
  490. #define CONFIG_SYS_HID0_INIT 0x000000000
  491. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  492. | HID0_ENABLE_INSTRUCTION_CACHE)
  493. /* #define CONFIG_SYS_HID0_FINAL (\
  494. HID0_ENABLE_INSTRUCTION_CACHE |\
  495. HID0_ENABLE_M_BIT |\
  496. HID0_ENABLE_ADDRESS_BROADCAST) */
  497. #define CONFIG_SYS_HID2 HID2_HBE
  498. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  499. /* DDR @ 0x00000000 */
  500. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  501. | BATL_PP_RW \
  502. | BATL_MEMCOHERENCE)
  503. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  504. | BATU_BL_256M \
  505. | BATU_VS \
  506. | BATU_VP)
  507. /* PCI @ 0x80000000 */
  508. #ifdef CONFIG_PCI
  509. #define CONFIG_PCI_INDIRECT_BRIDGE
  510. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  511. | BATL_PP_RW \
  512. | BATL_MEMCOHERENCE)
  513. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  514. | BATU_BL_256M \
  515. | BATU_VS \
  516. | BATU_VP)
  517. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  518. | BATL_PP_RW \
  519. | BATL_CACHEINHIBIT \
  520. | BATL_GUARDEDSTORAGE)
  521. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  522. | BATU_BL_256M \
  523. | BATU_VS \
  524. | BATU_VP)
  525. #else
  526. #define CONFIG_SYS_IBAT1L (0)
  527. #define CONFIG_SYS_IBAT1U (0)
  528. #define CONFIG_SYS_IBAT2L (0)
  529. #define CONFIG_SYS_IBAT2U (0)
  530. #endif
  531. #ifdef CONFIG_MPC83XX_PCI2
  532. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  533. | BATL_PP_RW \
  534. | BATL_MEMCOHERENCE)
  535. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  536. | BATU_BL_256M \
  537. | BATU_VS \
  538. | BATU_VP)
  539. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  540. | BATL_PP_RW \
  541. | BATL_CACHEINHIBIT \
  542. | BATL_GUARDEDSTORAGE)
  543. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  544. | BATU_BL_256M \
  545. | BATU_VS \
  546. | BATU_VP)
  547. #else
  548. #define CONFIG_SYS_IBAT3L (0)
  549. #define CONFIG_SYS_IBAT3U (0)
  550. #define CONFIG_SYS_IBAT4L (0)
  551. #define CONFIG_SYS_IBAT4U (0)
  552. #endif
  553. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  554. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  555. | BATL_PP_RW \
  556. | BATL_CACHEINHIBIT \
  557. | BATL_GUARDEDSTORAGE)
  558. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  559. | BATU_BL_256M \
  560. | BATU_VS \
  561. | BATU_VP)
  562. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  563. #define CONFIG_SYS_IBAT6L (0xF0000000 \
  564. | BATL_PP_RW \
  565. | BATL_MEMCOHERENCE \
  566. | BATL_GUARDEDSTORAGE)
  567. #define CONFIG_SYS_IBAT6U (0xF0000000 \
  568. | BATU_BL_256M \
  569. | BATU_VS \
  570. | BATU_VP)
  571. #define CONFIG_SYS_IBAT7L (0)
  572. #define CONFIG_SYS_IBAT7U (0)
  573. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  574. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  575. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  576. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  577. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  578. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  579. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  580. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  581. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  582. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  583. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  584. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  585. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  586. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  587. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  588. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  589. #if defined(CONFIG_CMD_KGDB)
  590. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  591. #endif
  592. /*
  593. * Environment Configuration
  594. */
  595. #define CONFIG_ENV_OVERWRITE
  596. #if defined(CONFIG_TSEC_ENET)
  597. #define CONFIG_HAS_ETH1
  598. #define CONFIG_HAS_ETH0
  599. #endif
  600. #define CONFIG_HOSTNAME "mpc8349emds"
  601. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  602. #define CONFIG_BOOTFILE "uImage"
  603. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  604. #define CONFIG_PREBOOT "echo;" \
  605. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  606. "echo"
  607. #define CONFIG_EXTRA_ENV_SETTINGS \
  608. "netdev=eth0\0" \
  609. "hostname=mpc8349emds\0" \
  610. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  611. "nfsroot=${serverip}:${rootpath}\0" \
  612. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  613. "addip=setenv bootargs ${bootargs} " \
  614. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  615. ":${hostname}:${netdev}:off panic=1\0" \
  616. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  617. "flash_nfs=run nfsargs addip addtty;" \
  618. "bootm ${kernel_addr}\0" \
  619. "flash_self=run ramargs addip addtty;" \
  620. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  621. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  622. "bootm\0" \
  623. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  624. "update=protect off fe000000 fe03ffff; " \
  625. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
  626. "upd=run load update\0" \
  627. "fdtaddr=780000\0" \
  628. "fdtfile=mpc834x_mds.dtb\0" \
  629. ""
  630. #define CONFIG_NFSBOOTCOMMAND \
  631. "setenv bootargs root=/dev/nfs rw " \
  632. "nfsroot=$serverip:$rootpath " \
  633. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  634. "$netdev:off " \
  635. "console=$consoledev,$baudrate $othbootargs;" \
  636. "tftp $loadaddr $bootfile;" \
  637. "tftp $fdtaddr $fdtfile;" \
  638. "bootm $loadaddr - $fdtaddr"
  639. #define CONFIG_RAMBOOTCOMMAND \
  640. "setenv bootargs root=/dev/ram rw " \
  641. "console=$consoledev,$baudrate $othbootargs;" \
  642. "tftp $ramdiskaddr $ramdiskfile;" \
  643. "tftp $loadaddr $bootfile;" \
  644. "tftp $fdtaddr $fdtfile;" \
  645. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  646. #define CONFIG_BOOTCOMMAND "run flash_self"
  647. #endif /* __CONFIG_H */