MPC8313ERDB.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  4. */
  5. /*
  6. * mpc8313epb board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1
  14. #define CONFIG_MPC831x 1
  15. #define CONFIG_MPC8313 1
  16. #define CONFIG_MPC8313ERDB 1
  17. #ifdef CONFIG_NAND
  18. #define CONFIG_SPL_INIT_MINIMAL
  19. #define CONFIG_SPL_FLUSH_IMAGE
  20. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  21. #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  22. #ifdef CONFIG_SPL_BUILD
  23. #define CONFIG_NS16550_MIN_FUNCTIONS
  24. #endif
  25. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  26. #define CONFIG_SPL_MAX_SIZE (4 * 1024)
  27. #define CONFIG_SPL_PAD_TO 0x4000
  28. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  29. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  30. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  31. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  32. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  33. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  34. #ifdef CONFIG_SPL_BUILD
  35. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  36. #endif
  37. #endif /* CONFIG_NAND */
  38. #ifndef CONFIG_SYS_MONITOR_BASE
  39. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  40. #endif
  41. #define CONFIG_PCI_INDIRECT_BRIDGE
  42. #define CONFIG_FSL_ELBC 1
  43. #define CONFIG_MISC_INIT_R
  44. /*
  45. * On-board devices
  46. *
  47. * TSEC1 is VSC switch
  48. * TSEC2 is SoC TSEC
  49. */
  50. #define CONFIG_VSC7385_ENET
  51. #define CONFIG_TSEC2
  52. #ifdef CONFIG_SYS_66MHZ
  53. #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
  54. #elif defined(CONFIG_SYS_33MHZ)
  55. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  56. #else
  57. #error Unknown oscillator frequency.
  58. #endif
  59. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  60. #define CONFIG_SYS_IMMR 0xE0000000
  61. #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  62. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  63. #endif
  64. #define CONFIG_SYS_MEMTEST_START 0x00001000
  65. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  66. /* Early revs of this board will lock up hard when attempting
  67. * to access the PMC registers, unless a JTAG debugger is
  68. * connected, or some resistor modifications are made.
  69. */
  70. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  71. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  72. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  73. /*
  74. * Device configurations
  75. */
  76. /* Vitesse 7385 */
  77. #ifdef CONFIG_VSC7385_ENET
  78. #define CONFIG_TSEC1
  79. /* The flash address and size of the VSC7385 firmware image */
  80. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  81. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  82. #endif
  83. /*
  84. * DDR Setup
  85. */
  86. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  87. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  88. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  89. /*
  90. * Manually set up DDR parameters, as this board does not
  91. * seem to have the SPD connected to I2C.
  92. */
  93. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  94. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  95. | CSCONFIG_ODT_RD_NEVER \
  96. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  97. | CSCONFIG_ROW_BIT_13 \
  98. | CSCONFIG_COL_BIT_10)
  99. /* 0x80010102 */
  100. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  101. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  102. | (0 << TIMING_CFG0_WRT_SHIFT) \
  103. | (0 << TIMING_CFG0_RRT_SHIFT) \
  104. | (0 << TIMING_CFG0_WWT_SHIFT) \
  105. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  106. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  107. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  108. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  109. /* 0x00220802 */
  110. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  111. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  112. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  113. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  114. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  115. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  116. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  117. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  118. /* 0x3835a322 */
  119. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  120. | (5 << TIMING_CFG2_CPO_SHIFT) \
  121. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  122. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  123. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  124. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  125. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  126. /* 0x129048c6 */ /* P9-45,may need tuning */
  127. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  128. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  129. /* 0x05100500 */
  130. #if defined(CONFIG_DDR_2T_TIMING)
  131. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  132. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  133. | SDRAM_CFG_DBW_32 \
  134. | SDRAM_CFG_2T_EN)
  135. /* 0x43088000 */
  136. #else
  137. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  138. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  139. | SDRAM_CFG_DBW_32)
  140. /* 0x43080000 */
  141. #endif
  142. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  143. /* set burst length to 8 for 32-bit data path */
  144. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  145. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  146. /* 0x44480632 */
  147. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  148. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  149. /*0x02000000*/
  150. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  151. | DDRCDR_PZ_NOMZ \
  152. | DDRCDR_NZ_NOMZ \
  153. | DDRCDR_M_ODR)
  154. /*
  155. * FLASH on the Local Bus
  156. */
  157. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  158. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  159. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  160. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  161. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  162. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  163. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  164. #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
  165. | BR_PS_16 /* 16 bit port */ \
  166. | BR_MS_GPCM /* MSEL = GPCM */ \
  167. | BR_V) /* valid */
  168. #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  169. | OR_GPCM_XACS \
  170. | OR_GPCM_SCY_9 \
  171. | OR_GPCM_EHTR \
  172. | OR_GPCM_EAD)
  173. /* 0xFF006FF7 TODO SLOW 16 MB flash size */
  174. /* window base at flash base */
  175. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  176. /* 16 MB window size */
  177. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
  178. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  179. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  180. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  181. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  182. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  183. !defined(CONFIG_SPL_BUILD)
  184. #define CONFIG_SYS_RAMBOOT
  185. #endif
  186. #define CONFIG_SYS_INIT_RAM_LOCK 1
  187. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  188. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  189. #define CONFIG_SYS_GBL_DATA_OFFSET \
  190. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  191. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  192. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  193. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  194. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  195. /*
  196. * Local Bus LCRR and LBCR regs
  197. */
  198. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  199. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  200. #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
  201. | (0xFF << LBCR_BMT_SHIFT) \
  202. | 0xF) /* 0x0004ff0f */
  203. /* LB refresh timer prescal, 266MHz/32 */
  204. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
  205. /* drivers/mtd/nand/nand.c */
  206. #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
  207. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  208. #else
  209. #define CONFIG_SYS_NAND_BASE 0xE2800000
  210. #endif
  211. #define CONFIG_MTD_DEVICE
  212. #define CONFIG_MTD_PARTITION
  213. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  214. #define CONFIG_NAND_FSL_ELBC 1
  215. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  216. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  217. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
  218. | BR_DECC_CHK_GEN /* Use HW ECC */ \
  219. | BR_PS_8 /* 8 bit port */ \
  220. | BR_MS_FCM /* MSEL = FCM */ \
  221. | BR_V) /* valid */
  222. #define CONFIG_SYS_NAND_OR_PRELIM \
  223. (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
  224. | OR_FCM_CSCT \
  225. | OR_FCM_CST \
  226. | OR_FCM_CHT \
  227. | OR_FCM_SCY_1 \
  228. | OR_FCM_TRLX \
  229. | OR_FCM_EHTR)
  230. /* 0xFFFF8396 */
  231. #ifdef CONFIG_NAND
  232. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  233. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  234. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  235. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  236. #else
  237. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  238. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  239. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  240. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  241. #endif
  242. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  243. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  244. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  245. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  246. /* local bus write LED / read status buffer (BCSR) mapping */
  247. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  248. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  249. /* map at 0xFA000000 on LCS3 */
  250. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
  251. | BR_PS_8 /* 8 bit port */ \
  252. | BR_MS_GPCM /* MSEL = GPCM */ \
  253. | BR_V) /* valid */
  254. /* 0xFA000801 */
  255. #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
  256. | OR_GPCM_CSNT \
  257. | OR_GPCM_ACS_DIV2 \
  258. | OR_GPCM_XACS \
  259. | OR_GPCM_SCY_15 \
  260. | OR_GPCM_TRLX_SET \
  261. | OR_GPCM_EHTR_SET \
  262. | OR_GPCM_EAD)
  263. /* 0xFFFF8FF7 */
  264. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
  265. #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  266. /* Vitesse 7385 */
  267. #ifdef CONFIG_VSC7385_ENET
  268. /* VSC7385 Base address on LCS2 */
  269. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  270. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  271. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
  272. | BR_PS_8 /* 8 bit port */ \
  273. | BR_MS_GPCM /* MSEL = GPCM */ \
  274. | BR_V) /* valid */
  275. #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
  276. | OR_GPCM_CSNT \
  277. | OR_GPCM_XACS \
  278. | OR_GPCM_SCY_15 \
  279. | OR_GPCM_SETA \
  280. | OR_GPCM_TRLX_SET \
  281. | OR_GPCM_EHTR_SET \
  282. | OR_GPCM_EAD)
  283. /* 0xFFFE09FF */
  284. /* Access window base at VSC7385 base */
  285. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
  286. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
  287. #endif
  288. #define CONFIG_MPC83XX_GPIO 1
  289. /*
  290. * Serial Port
  291. */
  292. #define CONFIG_SYS_NS16550_SERIAL
  293. #define CONFIG_SYS_NS16550_REG_SIZE 1
  294. #define CONFIG_SYS_BAUDRATE_TABLE \
  295. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  296. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  297. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  298. /* I2C */
  299. #define CONFIG_SYS_I2C
  300. #define CONFIG_SYS_I2C_FSL
  301. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  302. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  303. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  304. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  305. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  306. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  307. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  308. /*
  309. * General PCI
  310. * Addresses are mapped 1-1.
  311. */
  312. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  313. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  314. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  315. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  316. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  317. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  318. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  319. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  320. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  321. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  322. /*
  323. * TSEC
  324. */
  325. #define CONFIG_GMII /* MII PHY management */
  326. #ifdef CONFIG_TSEC1
  327. #define CONFIG_HAS_ETH0
  328. #define CONFIG_TSEC1_NAME "TSEC0"
  329. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  330. #define TSEC1_PHY_ADDR 0x1c
  331. #define TSEC1_FLAGS TSEC_GIGABIT
  332. #define TSEC1_PHYIDX 0
  333. #endif
  334. #ifdef CONFIG_TSEC2
  335. #define CONFIG_HAS_ETH1
  336. #define CONFIG_TSEC2_NAME "TSEC1"
  337. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  338. #define TSEC2_PHY_ADDR 4
  339. #define TSEC2_FLAGS TSEC_GIGABIT
  340. #define TSEC2_PHYIDX 0
  341. #endif
  342. /* Options are: TSEC[0-1] */
  343. #define CONFIG_ETHPRIME "TSEC1"
  344. /*
  345. * Configure on-board RTC
  346. */
  347. #define CONFIG_RTC_DS1337
  348. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  349. /*
  350. * Environment
  351. */
  352. #if defined(CONFIG_NAND)
  353. #define CONFIG_ENV_OFFSET (512 * 1024)
  354. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  355. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  356. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  357. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  358. #define CONFIG_ENV_OFFSET_REDUND \
  359. (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  360. #elif !defined(CONFIG_SYS_RAMBOOT)
  361. #define CONFIG_ENV_ADDR \
  362. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  363. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  364. #define CONFIG_ENV_SIZE 0x2000
  365. /* Address and size of Redundant Environment Sector */
  366. #else
  367. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  368. #define CONFIG_ENV_SIZE 0x2000
  369. #endif
  370. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  371. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  372. /*
  373. * BOOTP options
  374. */
  375. #define CONFIG_BOOTP_BOOTFILESIZE
  376. /*
  377. * Command line configuration.
  378. */
  379. /*
  380. * Miscellaneous configurable options
  381. */
  382. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  383. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  384. /* Boot Argument Buffer Size */
  385. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  386. /*
  387. * For booting Linux, the board info and command line data
  388. * have to be in the first 256 MB of memory, since this is
  389. * the maximum mapped by the Linux kernel during initialization.
  390. */
  391. /* Initial Memory map for Linux*/
  392. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  393. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  394. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  395. #ifdef CONFIG_SYS_66MHZ
  396. /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
  397. /* 0x62040000 */
  398. #define CONFIG_SYS_HRCW_LOW (\
  399. 0x20000000 /* reserved, must be set */ |\
  400. HRCWL_DDRCM |\
  401. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  402. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  403. HRCWL_CSB_TO_CLKIN_2X1 |\
  404. HRCWL_CORE_TO_CSB_2X1)
  405. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  406. #elif defined(CONFIG_SYS_33MHZ)
  407. /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
  408. /* 0x65040000 */
  409. #define CONFIG_SYS_HRCW_LOW (\
  410. 0x20000000 /* reserved, must be set */ |\
  411. HRCWL_DDRCM |\
  412. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  413. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  414. HRCWL_CSB_TO_CLKIN_5X1 |\
  415. HRCWL_CORE_TO_CSB_2X1)
  416. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
  417. #endif
  418. #define CONFIG_SYS_HRCW_HIGH_BASE (\
  419. HRCWH_PCI_HOST |\
  420. HRCWH_PCI1_ARBITER_ENABLE |\
  421. HRCWH_CORE_ENABLE |\
  422. HRCWH_BOOTSEQ_DISABLE |\
  423. HRCWH_SW_WATCHDOG_DISABLE |\
  424. HRCWH_TSEC1M_IN_RGMII |\
  425. HRCWH_TSEC2M_IN_RGMII |\
  426. HRCWH_BIG_ENDIAN)
  427. #ifdef CONFIG_NAND
  428. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  429. HRCWH_FROM_0XFFF00100 |\
  430. HRCWH_ROM_LOC_NAND_SP_8BIT |\
  431. HRCWH_RL_EXT_NAND)
  432. #else
  433. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  434. HRCWH_FROM_0X00000100 |\
  435. HRCWH_ROM_LOC_LOCAL_16BIT |\
  436. HRCWH_RL_EXT_LEGACY)
  437. #endif
  438. /* System IO Config */
  439. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  440. /* Enable Internal USB Phy and GPIO on LCD Connector */
  441. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  442. #define CONFIG_SYS_HID0_INIT 0x000000000
  443. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  444. HID0_ENABLE_INSTRUCTION_CACHE | \
  445. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  446. #define CONFIG_SYS_HID2 HID2_HBE
  447. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  448. /* DDR @ 0x00000000 */
  449. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
  450. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  451. | BATU_BL_256M \
  452. | BATU_VS \
  453. | BATU_VP)
  454. /* PCI @ 0x80000000 */
  455. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
  456. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  457. | BATU_BL_256M \
  458. | BATU_VS \
  459. | BATU_VP)
  460. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  461. | BATL_PP_RW \
  462. | BATL_CACHEINHIBIT \
  463. | BATL_GUARDEDSTORAGE)
  464. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  465. | BATU_BL_256M \
  466. | BATU_VS \
  467. | BATU_VP)
  468. /* PCI2 not supported on 8313 */
  469. #define CONFIG_SYS_IBAT3L (0)
  470. #define CONFIG_SYS_IBAT3U (0)
  471. #define CONFIG_SYS_IBAT4L (0)
  472. #define CONFIG_SYS_IBAT4U (0)
  473. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  474. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  475. | BATL_PP_RW \
  476. | BATL_CACHEINHIBIT \
  477. | BATL_GUARDEDSTORAGE)
  478. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  479. | BATU_BL_256M \
  480. | BATU_VS \
  481. | BATU_VP)
  482. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  483. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  484. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  485. #define CONFIG_SYS_IBAT7L (0)
  486. #define CONFIG_SYS_IBAT7U (0)
  487. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  488. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  489. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  490. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  491. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  492. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  493. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  494. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  495. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  496. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  497. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  498. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  499. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  500. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  501. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  502. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  503. /*
  504. * Environment Configuration
  505. */
  506. #define CONFIG_ENV_OVERWRITE
  507. #define CONFIG_NETDEV "eth1"
  508. #define CONFIG_HOSTNAME "mpc8313erdb"
  509. #define CONFIG_ROOTPATH "/nfs/root/path"
  510. #define CONFIG_BOOTFILE "uImage"
  511. /* U-Boot image on TFTP server */
  512. #define CONFIG_UBOOTPATH "u-boot.bin"
  513. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  514. /* default location for tftp and bootm */
  515. #define CONFIG_LOADADDR 800000
  516. #define CONFIG_EXTRA_ENV_SETTINGS \
  517. "netdev=" CONFIG_NETDEV "\0" \
  518. "ethprime=TSEC1\0" \
  519. "uboot=" CONFIG_UBOOTPATH "\0" \
  520. "tftpflash=tftpboot $loadaddr $uboot; " \
  521. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  522. " +$filesize; " \
  523. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  524. " +$filesize; " \
  525. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  526. " $filesize; " \
  527. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  528. " +$filesize; " \
  529. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  530. " $filesize\0" \
  531. "fdtaddr=780000\0" \
  532. "fdtfile=" CONFIG_FDTFILE "\0" \
  533. "console=ttyS0\0" \
  534. "setbootargs=setenv bootargs " \
  535. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  536. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  537. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  538. "$netdev:off " \
  539. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  540. #define CONFIG_NFSBOOTCOMMAND \
  541. "setenv rootdev /dev/nfs;" \
  542. "run setbootargs;" \
  543. "run setipargs;" \
  544. "tftp $loadaddr $bootfile;" \
  545. "tftp $fdtaddr $fdtfile;" \
  546. "bootm $loadaddr - $fdtaddr"
  547. #define CONFIG_RAMBOOTCOMMAND \
  548. "setenv rootdev /dev/ram;" \
  549. "run setbootargs;" \
  550. "tftp $ramdiskaddr $ramdiskfile;" \
  551. "tftp $loadaddr $bootfile;" \
  552. "tftp $fdtaddr $fdtfile;" \
  553. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  554. #endif /* __CONFIG_H */