M5485EVB.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5485 FireEngine board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5485EVB_H
  12. #define _M5485EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_HW_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. #define CONFIG_SLTTMR
  22. #define CONFIG_FSLDMAFEC
  23. #ifdef CONFIG_FSLDMAFEC
  24. # define CONFIG_MII 1
  25. # define CONFIG_MII_INIT 1
  26. # define CONFIG_HAS_ETH1
  27. # define CONFIG_SYS_DMA_USE_INTSRAM 1
  28. # define CONFIG_SYS_DISCOVER_PHY
  29. # define CONFIG_SYS_RX_ETH_BUFFER 32
  30. # define CONFIG_SYS_TX_ETH_BUFFER 48
  31. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  32. # define CONFIG_SYS_FEC0_PINMUX 0
  33. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  34. # define CONFIG_SYS_FEC1_PINMUX 0
  35. # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
  36. # define MCFFEC_TOUT_LOOP 50000
  37. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  38. # ifndef CONFIG_SYS_DISCOVER_PHY
  39. # define FECDUPLEX FULL
  40. # define FECSPEED _100BASET
  41. # else
  42. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44. # endif
  45. # endif /* CONFIG_SYS_DISCOVER_PHY */
  46. # define CONFIG_IPADDR 192.162.1.2
  47. # define CONFIG_NETMASK 255.255.255.0
  48. # define CONFIG_SERVERIP 192.162.1.1
  49. # define CONFIG_GATEWAYIP 192.162.1.1
  50. #endif
  51. #ifdef CONFIG_CMD_USB
  52. # define CONFIG_USB_OHCI_NEW
  53. /*# define CONFIG_PCI_OHCI*/
  54. # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
  55. # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  56. # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
  57. # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  58. #endif
  59. /* I2C */
  60. #define CONFIG_SYS_I2C
  61. #define CONFIG_SYS_I2C_FSL
  62. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  63. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  64. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
  65. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  66. /* PCI */
  67. #ifdef CONFIG_CMD_PCI
  68. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  69. #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
  70. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  71. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  72. #define CONFIG_SYS_PCI_IO_BUS 0x71000000
  73. #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
  74. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
  75. #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
  76. #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
  77. #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
  78. #endif
  79. #define CONFIG_UDP_CHECKSUM
  80. #define CONFIG_HOSTNAME "M548xEVB"
  81. #define CONFIG_EXTRA_ENV_SETTINGS \
  82. "netdev=eth0\0" \
  83. "loadaddr=10000\0" \
  84. "u-boot=u-boot.bin\0" \
  85. "load=tftp ${loadaddr) ${u-boot}\0" \
  86. "upd=run load; run prog\0" \
  87. "prog=prot off bank 1;" \
  88. "era ff800000 ff83ffff;" \
  89. "cp.b ${loadaddr} ff800000 ${filesize};"\
  90. "save\0" \
  91. ""
  92. #define CONFIG_PRAM 512 /* 512 KB */
  93. #define CONFIG_SYS_LOAD_ADDR 0x00010000
  94. #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
  95. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  96. #define CONFIG_SYS_MBAR 0xF0000000
  97. #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
  98. #define CONFIG_SYS_INTSRAMSZ 0x8000
  99. /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
  100. /*
  101. * Low Level Configuration Settings
  102. * (address mappings, register initial values, etc.)
  103. * You should know what you are doing if you make changes here.
  104. */
  105. /*-----------------------------------------------------------------------
  106. * Definitions for initial stack pointer and data area (in DPRAM)
  107. */
  108. #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
  109. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  110. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  111. #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  112. #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
  113. #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
  114. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  115. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  116. /*-----------------------------------------------------------------------
  117. * Start addresses for the final memory configuration
  118. * (Set up by the startup code)
  119. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  120. */
  121. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  122. #define CONFIG_SYS_SDRAM_CFG1 0x73711630
  123. #define CONFIG_SYS_SDRAM_CFG2 0x46770000
  124. #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
  125. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  126. #define CONFIG_SYS_SDRAM_MODE 0x018D0000
  127. #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
  128. #ifdef CONFIG_SYS_DRAMSZ1
  129. # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
  130. #else
  131. # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
  132. #endif
  133. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  134. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  135. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  136. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  137. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  138. /* Reserve 256 kB for malloc() */
  139. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  140. /*
  141. * For booting Linux, the board info and command line data
  142. * have to be in the first 8 MB of memory, since this is
  143. * the maximum mapped by the Linux kernel during initialization ??
  144. */
  145. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  146. /*-----------------------------------------------------------------------
  147. * FLASH organization
  148. */
  149. #define CONFIG_SYS_FLASH_CFI
  150. #ifdef CONFIG_SYS_FLASH_CFI
  151. # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  152. # define CONFIG_FLASH_CFI_DRIVER 1
  153. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  154. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  155. # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  156. # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  157. #ifdef CONFIG_SYS_NOR1SZ
  158. # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  159. # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
  160. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
  161. #else
  162. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  163. # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
  164. #endif
  165. #endif
  166. /* Configuration for environment
  167. * Environment is not embedded in u-boot. First time runing may have env
  168. * crc error warning if there is no correct environment on the flash.
  169. */
  170. #define CONFIG_ENV_OFFSET 0x40000
  171. #define CONFIG_ENV_SECT_SIZE 0x10000
  172. /*-----------------------------------------------------------------------
  173. * Cache Configuration
  174. */
  175. #define CONFIG_SYS_CACHELINE_SIZE 16
  176. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  177. CONFIG_SYS_INIT_RAM_SIZE - 8)
  178. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  179. CONFIG_SYS_INIT_RAM_SIZE - 4)
  180. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
  181. CF_CACR_IDCM)
  182. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  183. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  184. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  185. CF_ACR_EN | CF_ACR_SM_ALL)
  186. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
  187. CF_CACR_IEC | CF_CACR_ICINVA)
  188. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  189. CF_CACR_DEC | CF_CACR_DDCM_P | \
  190. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  191. /*-----------------------------------------------------------------------
  192. * Chipselect bank definitions
  193. */
  194. /*
  195. * CS0 - NOR Flash 1, 2, 4, or 8MB
  196. * CS1 - NOR Flash
  197. * CS2 - Available
  198. * CS3 - Available
  199. * CS4 - Available
  200. * CS5 - Available
  201. */
  202. #define CONFIG_SYS_CS0_BASE 0xFF800000
  203. #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
  204. #define CONFIG_SYS_CS0_CTRL 0x00101980
  205. #ifdef CONFIG_SYS_NOR1SZ
  206. #define CONFIG_SYS_CS1_BASE 0xE0000000
  207. #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
  208. #define CONFIG_SYS_CS1_CTRL 0x00101D80
  209. #endif
  210. #endif /* _M5485EVB_H */